forked from OSchip/llvm-project
94 lines
3.4 KiB
YAML
94 lines
3.4 KiB
YAML
# Check that the backend can handle consecutive select instructions also in
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# the presence of DEBUG_VALUE machine instructions.
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#
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# RUN: llc %s -verify-machineinstrs -mtriple=s390x-linux-gnu -mcpu=z13 \
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# RUN: -start-before=expand-isel-pseudos -o - 2>&1 | FileCheck %s
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#
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# CHECK-LABEL: %bb.1:
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# CHECK: ldr
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# CHECK-NEXT: ldr
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# CHECK-NEXT: ldr
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--- |
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; ModuleID = 'tc.ll'
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source_filename = "tc.ll"
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target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"
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define float @fun(i1 %cmp, float %arg0, float %arg1, float %arg2, float %arg3, float %arg4) #0 {
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%fs0 = select i1 %cmp, float %arg0, float %arg1
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; Keep the dbg metadata live by referencing it in the IR.
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call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !7, metadata !DIExpression()), !dbg !9
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%fs1 = select i1 %cmp, float %arg2, float %arg3
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call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !7, metadata !DIExpression()), !dbg !9
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%fs2 = select i1 %cmp, float %arg0, float %arg3
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%s0 = fadd float %fs0, %fs1
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%s1 = fadd float %s0, %fs2
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ret float %s1
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}
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declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
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attributes #0 = { "target-cpu"="z13" }
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!llvm.dbg.cu = !{!0}
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!llvm.module.flags = !{!3, !4}
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!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "llvm", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
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!1 = !DIFile(filename: "test.ll", directory: "/tmp")
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!2 = !{}
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!3 = !{i32 2, !"Dwarf Version", i32 4}
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!4 = !{i32 2, !"Debug Info Version", i32 3}
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!5 = distinct !DISubprogram(name: "test_dbg_value", scope: !1, file: !1, line: 1, type: !6, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, retainedNodes: !2)
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!6 = !DISubroutineType(types: !2)
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!7 = !DILocalVariable(name: "in", arg: 1, scope: !5, file: !1, line: 1, type: !8)
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!8 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
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!9 = !DILocation(line: 1, column: 1, scope: !5)
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...
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---
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name: fun
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr32bit }
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- { id: 1, class: fp32bit }
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- { id: 2, class: fp32bit }
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- { id: 3, class: fp32bit }
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- { id: 4, class: fp32bit }
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- { id: 5, class: fp32bit }
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- { id: 6, class: fp32bit }
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- { id: 7, class: fp32bit }
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- { id: 8, class: fp32bit }
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- { id: 9, class: fp32bit }
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liveins:
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- { reg: '$r2l', virtual-reg: '%0' }
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- { reg: '$f0s', virtual-reg: '%1' }
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- { reg: '$f2s', virtual-reg: '%2' }
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- { reg: '$f4s', virtual-reg: '%3' }
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- { reg: '$f6s', virtual-reg: '%4' }
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frameInfo:
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maxAlignment: 8
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fixedStack:
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- { id: 0, size: 4, alignment: 8, stack-id: 0, isImmutable: true }
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body: |
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bb.0 (%ir-block.0):
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liveins: $r2l, $f0s, $f2s, $f4s, $f6s
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%4:fp32bit = COPY $f6s
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%3:fp32bit = COPY $f4s
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%2:fp32bit = COPY $f2s
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%1:fp32bit = COPY $f0s
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%0:gr32bit = COPY $r2l
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TMLMux %0, 1, implicit-def $cc
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%5:fp32bit = SelectVR32 %1, %2, 15, 7, implicit $cc
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DBG_VALUE %5, $noreg, !7, !DIExpression(), debug-location !9
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%6:fp32bit = SelectVR32 %3, %4, 15, 7, implicit $cc
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DBG_VALUE %6, $noreg, !7, !DIExpression(), debug-location !9
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%7:fp32bit = SelectVR32 %1, %4, 15, 7, implicit $cc
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%8:fp32bit = AEBR %5, killed %6, implicit-def dead $cc
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%9:fp32bit = AEBR %8, killed %7, implicit-def dead $cc
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$f0s = COPY %9
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Return implicit $f0s
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...
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