forked from OSchip/llvm-project
bc6d07ca46
This has been a very painful missing feature that has made producing reduced testcases difficult. In particular the various registers determined for stack access during function lowering were necessary to avoid undefined register errors in a large percentage of cases. Implement a subset of the important fields that need to be preserved for AMDGPU. Most of the changes are to support targets parsing register fields and properly reporting errors. The biggest sort-of bug remaining is for fields that can be initialized from the IR section will be overwritten by a default initialized machineFunctionInfo section. Another remaining bug is the machineFunctionInfo section is still printed even if empty. llvm-svn: 356215 |
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| .. | ||
| AArch64 | ||
| AMDGPU | ||
| ARM | ||
| Generic | ||
| Hexagon | ||
| Mips | ||
| NVPTX | ||
| PowerPC | ||
| WebAssembly | ||
| X86 | ||
| README | ||
README
This directory contains tests for the MIR file format parser and printer. It was necessary to split the tests across different targets as no single target covers all features available in machine IR. Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As a rule of thumb this directory should only contain tests using 'llc -run-pass none'.