forked from OSchip/llvm-project
216 lines
6.2 KiB
C
216 lines
6.2 KiB
C
// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +bmi -emit-llvm -o - -Wall -Werror | FileCheck %s
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#include <immintrin.h>
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// NOTE: This should match the tests in llvm/test/CodeGen/X86/bmi-intrinsics-fast-isel.ll
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// The double underscore intrinsics are for compatibility with
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// AMD's BMI interface. The single underscore intrinsics
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// are for compatibility with Intel's BMI interface.
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// Apart from the underscores, the interfaces are identical
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// except in one case: although the 'bextr' register-form
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// instruction is identical in hardware, the AMD and Intel
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// intrinsics are different!
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unsigned short test__tzcnt_u16(unsigned short __X) {
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// CHECK-LABEL: test__tzcnt_u16
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// CHECK: i16 @llvm.cttz.i16(i16 %{{.*}}, i1 false)
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return __tzcnt_u16(__X);
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}
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unsigned int test__andn_u32(unsigned int __X, unsigned int __Y) {
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// CHECK-LABEL: test__andn_u32
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// CHECK: xor i32 %{{.*}}, -1
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// CHECK: and i32 %{{.*}}, %{{.*}}
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return __andn_u32(__X, __Y);
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}
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unsigned int test__bextr_u32(unsigned int __X, unsigned int __Y) {
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// CHECK-LABEL: test__bextr_u32
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// CHECK: i32 @llvm.x86.bmi.bextr.32(i32 %{{.*}}, i32 %{{.*}})
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return __bextr_u32(__X, __Y);
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}
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unsigned int test__blsi_u32(unsigned int __X) {
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// CHECK-LABEL: test__blsi_u32
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// CHECK: sub i32 0, %{{.*}}
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// CHECK: and i32 %{{.*}}, %{{.*}}
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return __blsi_u32(__X);
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}
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unsigned int test__blsmsk_u32(unsigned int __X) {
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// CHECK-LABEL: test__blsmsk_u32
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// CHECK: sub i32 %{{.*}}, 1
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// CHECK: xor i32 %{{.*}}, %{{.*}}
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return __blsmsk_u32(__X);
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}
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unsigned int test__blsr_u32(unsigned int __X) {
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// CHECK-LABEL: test__blsr_u32
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// CHECK: sub i32 %{{.*}}, 1
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// CHECK: and i32 %{{.*}}, %{{.*}}
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return __blsr_u32(__X);
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}
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unsigned int test__tzcnt_u32(unsigned int __X) {
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// CHECK-LABEL: test__tzcnt_u32
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// CHECK: i32 @llvm.cttz.i32(i32 %{{.*}}, i1 false)
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return __tzcnt_u32(__X);
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}
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int test_mm_tzcnt_32(unsigned int __X) {
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// CHECK-LABEL: test_mm_tzcnt_32
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// CHECK: i32 @llvm.cttz.i32(i32 %{{.*}}, i1 false)
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return _mm_tzcnt_32(__X);
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}
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#ifdef __x86_64__
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unsigned long long test__andn_u64(unsigned long __X, unsigned long __Y) {
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// CHECK-LABEL: test__andn_u64
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// CHECK: xor i64 %{{.*}}, -1
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// CHECK: and i64 %{{.*}}, %{{.*}}
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return __andn_u64(__X, __Y);
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}
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unsigned long long test__bextr_u64(unsigned long __X, unsigned long __Y) {
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// CHECK-LABEL: test__bextr_u64
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// CHECK: i64 @llvm.x86.bmi.bextr.64(i64 %{{.*}}, i64 %{{.*}})
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return __bextr_u64(__X, __Y);
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}
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unsigned long long test__blsi_u64(unsigned long long __X) {
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// CHECK-LABEL: test__blsi_u64
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// CHECK: sub i64 0, %{{.*}}
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// CHECK: and i64 %{{.*}}, %{{.*}}
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return __blsi_u64(__X);
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}
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unsigned long long test__blsmsk_u64(unsigned long long __X) {
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// CHECK-LABEL: test__blsmsk_u64
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// CHECK: sub i64 %{{.*}}, 1
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// CHECK: xor i64 %{{.*}}, %{{.*}}
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return __blsmsk_u64(__X);
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}
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unsigned long long test__blsr_u64(unsigned long long __X) {
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// CHECK-LABEL: test__blsr_u64
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// CHECK: sub i64 %{{.*}}, 1
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// CHECK: and i64 %{{.*}}, %{{.*}}
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return __blsr_u64(__X);
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}
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unsigned long long test__tzcnt_u64(unsigned long long __X) {
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// CHECK-LABEL: test__tzcnt_u64
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// CHECK: i64 @llvm.cttz.i64(i64 %{{.*}}, i1 false)
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return __tzcnt_u64(__X);
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}
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long long test_mm_tzcnt_64(unsigned long long __X) {
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// CHECK-LABEL: test_mm_tzcnt_64
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// CHECK: i64 @llvm.cttz.i64(i64 %{{.*}}, i1 false)
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return _mm_tzcnt_64(__X);
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}
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#endif
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// Intel intrinsics
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unsigned short test_tzcnt_u16(unsigned short __X) {
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// CHECK-LABEL: test_tzcnt_u16
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// CHECK: i16 @llvm.cttz.i16(i16 %{{.*}}, i1 false)
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return _tzcnt_u16(__X);
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}
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unsigned int test_andn_u32(unsigned int __X, unsigned int __Y) {
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// CHECK-LABEL: test_andn_u32
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// CHECK: xor i32 %{{.*}}, -1
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// CHECK: and i32 %{{.*}}, %{{.*}}
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return _andn_u32(__X, __Y);
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}
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unsigned int test_bextr_u32(unsigned int __X, unsigned int __Y,
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unsigned int __Z) {
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// CHECK-LABEL: test_bextr_u32
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// CHECK: and i32 %{{.*}}, 255
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// CHECK: and i32 %{{.*}}, 255
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// CHECK: shl i32 %{{.*}}, 8
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// CHECK: or i32 %{{.*}}, %{{.*}}
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// CHECK: i32 @llvm.x86.bmi.bextr.32(i32 %{{.*}}, i32 %{{.*}})
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return _bextr_u32(__X, __Y, __Z);
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}
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unsigned int test_blsi_u32(unsigned int __X) {
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// CHECK-LABEL: test_blsi_u32
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// CHECK: sub i32 0, %{{.*}}
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// CHECK: and i32 %{{.*}}, %{{.*}}
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return _blsi_u32(__X);
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}
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unsigned int test_blsmsk_u32(unsigned int __X) {
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// CHECK-LABEL: test_blsmsk_u32
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// CHECK: sub i32 %{{.*}}, 1
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// CHECK: xor i32 %{{.*}}, %{{.*}}
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return _blsmsk_u32(__X);
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}
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unsigned int test_blsr_u32(unsigned int __X) {
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// CHECK-LABEL: test_blsr_u32
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// CHECK: sub i32 %{{.*}}, 1
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// CHECK: and i32 %{{.*}}, %{{.*}}
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return _blsr_u32(__X);
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}
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unsigned int test_tzcnt_u32(unsigned int __X) {
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// CHECK-LABEL: test_tzcnt_u32
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// CHECK: i32 @llvm.cttz.i32(i32 %{{.*}}, i1 false)
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return _tzcnt_u32(__X);
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}
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#ifdef __x86_64__
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unsigned long long test_andn_u64(unsigned long __X, unsigned long __Y) {
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// CHECK-LABEL: test_andn_u64
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// CHECK: xor i64 %{{.*}}, -1
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// CHECK: and i64 %{{.*}}, %{{.*}}
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return _andn_u64(__X, __Y);
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}
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unsigned long long test_bextr_u64(unsigned long __X, unsigned int __Y,
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unsigned int __Z) {
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// CHECK-LABEL: test_bextr_u64
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// CHECK: and i32 %{{.*}}, 255
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// CHECK: and i32 %{{.*}}, 255
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// CHECK: shl i32 %{{.*}}, 8
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// CHECK: or i32 %{{.*}}, %{{.*}}
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// CHECK: zext i32 %{{.*}} to i64
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// CHECK: i64 @llvm.x86.bmi.bextr.64(i64 %{{.*}}, i64 %{{.*}})
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return _bextr_u64(__X, __Y, __Z);
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}
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unsigned long long test_blsi_u64(unsigned long long __X) {
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// CHECK-LABEL: test_blsi_u64
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// CHECK: sub i64 0, %{{.*}}
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// CHECK: and i64 %{{.*}}, %{{.*}}
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return _blsi_u64(__X);
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}
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unsigned long long test_blsmsk_u64(unsigned long long __X) {
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// CHECK-LABEL: test_blsmsk_u64
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// CHECK: sub i64 %{{.*}}, 1
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// CHECK: xor i64 %{{.*}}, %{{.*}}
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return _blsmsk_u64(__X);
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}
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unsigned long long test_blsr_u64(unsigned long long __X) {
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// CHECK-LABEL: test_blsr_u64
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// CHECK: sub i64 %{{.*}}, 1
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// CHECK: and i64 %{{.*}}, %{{.*}}
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return _blsr_u64(__X);
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}
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unsigned long long test_tzcnt_u64(unsigned long long __X) {
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// CHECK-LABEL: test_tzcnt_u64
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// CHECK: i64 @llvm.cttz.i64(i64 %{{.*}}, i1 false)
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return _tzcnt_u64(__X);
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}
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#endif
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