forked from OSchip/llvm-project
299 lines
12 KiB
C++
299 lines
12 KiB
C++
//===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
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#define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
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#include "PPC.h"
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#include "PPCRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "PPCGenInstrInfo.inc"
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namespace llvm {
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/// PPCII - This namespace holds all of the PowerPC target-specific
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/// per-instruction flags. These must match the corresponding definitions in
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/// PPC.td and PPCInstrFormats.td.
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namespace PPCII {
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enum {
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// PPC970 Instruction Flags. These flags describe the characteristics of the
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// PowerPC 970 (aka G5) dispatch groups and how they are formed out of
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// raw machine instructions.
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/// PPC970_First - This instruction starts a new dispatch group, so it will
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/// always be the first one in the group.
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PPC970_First = 0x1,
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/// PPC970_Single - This instruction starts a new dispatch group and
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/// terminates it, so it will be the sole instruction in the group.
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PPC970_Single = 0x2,
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/// PPC970_Cracked - This instruction is cracked into two pieces, requiring
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/// two dispatch pipes to be available to issue.
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PPC970_Cracked = 0x4,
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/// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
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/// an instruction is issued to.
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PPC970_Shift = 3,
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PPC970_Mask = 0x07 << PPC970_Shift
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};
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enum PPC970_Unit {
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/// These are the various PPC970 execution unit pipelines. Each instruction
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/// is one of these.
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PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
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PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit
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PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit
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PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit
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PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit
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PPC970_VALU = 5 << PPC970_Shift, // Vector ALU
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PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit
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PPC970_BRU = 7 << PPC970_Shift // Branch Unit
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};
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enum {
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/// Shift count to bypass PPC970 flags
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NewDef_Shift = 6,
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/// The VSX instruction that uses VSX register (vs0-vs63), instead of VMX
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/// register (v0-v31).
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UseVSXReg = 0x1 << NewDef_Shift
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};
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} // end namespace PPCII
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class PPCSubtarget;
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class PPCInstrInfo : public PPCGenInstrInfo {
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PPCSubtarget &Subtarget;
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const PPCRegisterInfo RI;
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bool StoreRegToStackSlot(MachineFunction &MF,
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unsigned SrcReg, bool isKill, int FrameIdx,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs,
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bool &NonRI, bool &SpillsVRS) const;
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bool LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr *> &NewMIs,
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bool &NonRI, bool &SpillsVRS) const;
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virtual void anchor();
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protected:
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/// Commutes the operands in the given instruction.
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/// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
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///
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/// Do not call this method for a non-commutable instruction or for
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/// non-commutable pair of operand indices OpIdx1 and OpIdx2.
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/// Even though the instruction is commutable, the method may still
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/// fail to commute the operands, null pointer is returned in such cases.
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///
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/// For example, we can commute rlwimi instructions, but only if the
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/// rotate amt is zero. We also have to munge the immediates a bit.
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MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
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unsigned OpIdx1,
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unsigned OpIdx2) const override;
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public:
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explicit PPCInstrInfo(PPCSubtarget &STI);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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const PPCRegisterInfo &getRegisterInfo() const { return RI; }
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ScheduleHazardRecognizer *
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CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
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const ScheduleDAG *DAG) const override;
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ScheduleHazardRecognizer *
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CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
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const ScheduleDAG *DAG) const override;
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unsigned getInstrLatency(const InstrItineraryData *ItinData,
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const MachineInstr &MI,
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unsigned *PredCost = nullptr) const override;
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int getOperandLatency(const InstrItineraryData *ItinData,
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const MachineInstr &DefMI, unsigned DefIdx,
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const MachineInstr &UseMI,
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unsigned UseIdx) const override;
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int getOperandLatency(const InstrItineraryData *ItinData,
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SDNode *DefNode, unsigned DefIdx,
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SDNode *UseNode, unsigned UseIdx) const override {
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return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
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UseNode, UseIdx);
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}
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bool hasLowDefLatency(const TargetSchedModel &SchedModel,
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const MachineInstr &DefMI,
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unsigned DefIdx) const override {
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// Machine LICM should hoist all instructions in low-register-pressure
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// situations; none are sufficiently free to justify leaving in a loop
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// body.
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return false;
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}
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bool useMachineCombiner() const override {
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return true;
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}
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/// Return true when there is potentially a faster code sequence
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/// for an instruction chain ending in <Root>. All potential patterns are
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/// output in the <Pattern> array.
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bool getMachineCombinerPatterns(
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MachineInstr &Root,
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SmallVectorImpl<MachineCombinerPattern> &P) const override;
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bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
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bool isCoalescableExtInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SubIdx) const override;
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unsigned isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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unsigned isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
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unsigned &SrcOpIdx2) const override;
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void insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const override;
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// Branch analysis.
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const override;
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved = nullptr) const override;
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL,
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int *BytesAdded = nullptr) const override;
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// Select analysis.
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bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
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unsigned, unsigned, int &, int &, int &) const override;
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void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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const DebugLoc &DL, unsigned DstReg,
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ArrayRef<MachineOperand> Cond, unsigned TrueReg,
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unsigned FalseReg) const override;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const override;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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bool
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reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
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MachineRegisterInfo *MRI) const override;
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// If conversion by predication (only supported by some branch instructions).
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// All of the profitability checks always return true; it is always
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// profitable to use the predicated branches.
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bool isProfitableToIfCvt(MachineBasicBlock &MBB,
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unsigned NumCycles, unsigned ExtraPredCycles,
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BranchProbability Probability) const override {
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return true;
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}
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bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
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unsigned NumT, unsigned ExtraT,
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MachineBasicBlock &FMBB,
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unsigned NumF, unsigned ExtraF,
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BranchProbability Probability) const override;
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bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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BranchProbability Probability) const override {
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return true;
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}
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bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
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MachineBasicBlock &FMBB) const override {
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return false;
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}
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// Predication support.
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bool isPredicated(const MachineInstr &MI) const override;
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bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
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bool PredicateInstruction(MachineInstr &MI,
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ArrayRef<MachineOperand> Pred) const override;
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bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
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ArrayRef<MachineOperand> Pred2) const override;
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bool DefinesPredicate(MachineInstr &MI,
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std::vector<MachineOperand> &Pred) const override;
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bool isPredicable(const MachineInstr &MI) const override;
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// Comparison optimization.
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bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
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unsigned &SrcReg2, int &Mask, int &Value) const override;
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bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
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unsigned SrcReg2, int Mask, int Value,
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const MachineRegisterInfo *MRI) const override;
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/// GetInstSize - Return the number of bytes of code the specified
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/// instruction may be. This returns the maximum number of bytes.
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///
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unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
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void getNoop(MCInst &NopInst) const override;
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std::pair<unsigned, unsigned>
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decomposeMachineOperandsTargetFlags(unsigned TF) const override;
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ArrayRef<std::pair<unsigned, const char *>>
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getSerializableDirectMachineOperandTargetFlags() const override;
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ArrayRef<std::pair<unsigned, const char *>>
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getSerializableBitmaskMachineOperandTargetFlags() const override;
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// Lower pseudo instructions after register allocation.
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bool expandPostRAPseudo(MachineInstr &MI) const override;
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static bool isVFRegister(unsigned Reg) {
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return Reg >= PPC::VF0 && Reg <= PPC::VF31;
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}
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static bool isVRRegister(unsigned Reg) {
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return Reg >= PPC::V0 && Reg <= PPC::V31;
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}
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const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const;
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static int getRecordFormOpcode(unsigned Opcode);
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};
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}
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#endif
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