forked from OSchip/llvm-project
170 lines
7.1 KiB
LLVM
170 lines
7.1 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=kaveri -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,CIVI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,CIVI,GFX89 %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,GFX9 %s
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; FIXME: Should be able to do scalar op
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; GCN-LABEL: {{^}}s_fneg_f16:
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define amdgpu_kernel void @s_fneg_f16(half addrspace(1)* %out, half %in) #0 {
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%fneg = fsub half -0.0, %in
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store half %fneg, half addrspace(1)* %out
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ret void
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}
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; FIXME: Should be able to use bit operations when illegal type as
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; well.
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; GCN-LABEL: {{^}}v_fneg_f16:
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; GCN: {{flat|global}}_load_ushort [[VAL:v[0-9]+]],
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; GCN: v_xor_b32_e32 [[XOR:v[0-9]+]], 0x8000, [[VAL]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[XOR]]
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; SI: buffer_store_short [[XOR]]
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define amdgpu_kernel void @v_fneg_f16(half addrspace(1)* %out, half addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.in = getelementptr inbounds half, half addrspace(1)* %in, i32 %tid
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%gep.out = getelementptr inbounds half, half addrspace(1)* %in, i32 %tid
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%val = load half, half addrspace(1)* %gep.in, align 2
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%fneg = fsub half -0.0, %val
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store half %fneg, half addrspace(1)* %gep.out
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ret void
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}
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; GCN-LABEL: {{^}}fneg_free_f16:
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; GCN: {{flat|global}}_load_ushort [[NEG_VALUE:v[0-9]+]],
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; XCI: s_xor_b32 [[XOR:s[0-9]+]], [[NEG_VALUE]], 0x8000{{$}}
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; CI: v_xor_b32_e32 [[XOR:v[0-9]+]], 0x8000, [[NEG_VALUE]]
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; CI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[XOR]]
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define amdgpu_kernel void @fneg_free_f16(half addrspace(1)* %out, i16 %in) #0 {
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%bc = bitcast i16 %in to half
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%fsub = fsub half -0.0, %bc
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store half %fsub, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_fneg_fold_f16:
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; GCN: {{flat|global}}_load_ushort [[NEG_VALUE:v[0-9]+]]
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; CI-DAG: v_cvt_f32_f16_e32 [[CVT_VAL:v[0-9]+]], [[NEG_VALUE]]
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; CI-DAG: v_cvt_f32_f16_e64 [[NEG_CVT0:v[0-9]+]], -[[NEG_VALUE]]
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; CI: v_mul_f32_e32 [[MUL:v[0-9]+]], [[NEG_CVT0]], [[CVT_VAL]]
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; CI: v_cvt_f16_f32_e32 [[CVT1:v[0-9]+]], [[MUL]]
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; CI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[CVT1]]
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; VI-NOT: [[NEG_VALUE]]
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; VI: v_mul_f16_e64 v{{[0-9]+}}, -[[NEG_VALUE]], [[NEG_VALUE]]
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define amdgpu_kernel void @v_fneg_fold_f16(half addrspace(1)* %out, half addrspace(1)* %in) #0 {
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%val = load half, half addrspace(1)* %in
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%fsub = fsub half -0.0, %val
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%fmul = fmul half %fsub, %val
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store half %fmul, half addrspace(1)* %out
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ret void
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}
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; FIXME: Terrible code with SI/CI.
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; FIXME: scalar for VI, vector for gfx9
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; GCN-LABEL: {{^}}s_fneg_v2f16:
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; CI: s_mov_b32 [[MASK:s[0-9]+]], 0x8000{{$}}
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; CI: v_xor_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}}
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; CI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
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; CI: v_xor_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}}
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; CI: v_or_b32_e32
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; VI: s_xor_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80008000
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; GFX9: v_xor_b32_e32 v{{[0-9]+}}, 0x80008000, v{{[0-9]+}}
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define amdgpu_kernel void @s_fneg_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %in) #0 {
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%fneg = fsub <2 x half> <half -0.0, half -0.0>, %in
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store <2 x half> %fneg, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_fneg_v2f16:
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; GCN: {{flat|global}}_load_dword [[VAL:v[0-9]+]]
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; GCN: v_xor_b32_e32 v{{[0-9]+}}, 0x80008000, [[VAL]]
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define amdgpu_kernel void @v_fneg_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.in = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %in, i32 %tid
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%gep.out = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %in, i32 %tid
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%val = load <2 x half>, <2 x half> addrspace(1)* %gep.in, align 2
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%fneg = fsub <2 x half> <half -0.0, half -0.0>, %val
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store <2 x half> %fneg, <2 x half> addrspace(1)* %gep.out
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ret void
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}
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; GCN-LABEL: {{^}}fneg_free_v2f16:
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; GCN: s_load_dword [[VAL:s[0-9]+]]
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; CIVI: s_xor_b32 s{{[0-9]+}}, [[VAL]], 0x80008000
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; GFX9: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GFX9: v_xor_b32_e32 v{{[0-9]+}}, 0x80008000, [[VVAL]]
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define amdgpu_kernel void @fneg_free_v2f16(<2 x half> addrspace(1)* %out, i32 %in) #0 {
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%bc = bitcast i32 %in to <2 x half>
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%fsub = fsub <2 x half> <half -0.0, half -0.0>, %bc
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store <2 x half> %fsub, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_fneg_fold_v2f16:
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; GCN: {{flat|global}}_load_dword [[VAL:v[0-9]+]]
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; CI: v_cvt_f32_f16_e64 v{{[0-9]+}}, -v{{[0-9]+}}
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; CI: v_cvt_f32_f16_e64 v{{[0-9]+}}, -v{{[0-9]+}}
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; CI: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; CI: v_cvt_f16_f32
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; CI: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; CI: v_cvt_f16_f32
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; VI: v_mul_f16_sdwa v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; VI: v_mul_f16_e64 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}
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; GFX9: v_pk_mul_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} neg_lo:[1,0] neg_hi:[1,0]{{$}}
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define amdgpu_kernel void @v_fneg_fold_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 {
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%val = load <2 x half>, <2 x half> addrspace(1)* %in
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%fsub = fsub <2 x half> <half -0.0, half -0.0>, %val
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%fmul = fmul <2 x half> %fsub, %val
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store <2 x half> %fmul, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_extract_fneg_fold_v2f16:
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; GCN-DAG: {{flat|global}}_load_dword [[VAL:v[0-9]+]]
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; CI-DAG: v_mul_f32_e32 v{{[0-9]+}}, -4.0, v{{[0-9]+}}
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; CI-DAG: v_sub_f32_e32 v{{[0-9]+}}, 2.0, v{{[0-9]+}}
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; GFX89-DAG: v_mul_f16_e32 v{{[0-9]+}}, -4.0, [[VAL]]
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; GFX89-DAG: v_mov_b32_e32 [[CONST2:v[0-9]+]], 0x4000
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; GFX89-DAG: v_sub_f16_sdwa v{{[0-9]+}}, [[CONST2]], [[VAL]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
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define amdgpu_kernel void @v_extract_fneg_fold_v2f16(<2 x half> addrspace(1)* %in) #0 {
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%val = load <2 x half>, <2 x half> addrspace(1)* %in
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%fneg = fsub <2 x half> <half -0.0, half -0.0>, %val
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%elt0 = extractelement <2 x half> %fneg, i32 0
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%elt1 = extractelement <2 x half> %fneg, i32 1
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%fmul0 = fmul half %elt0, 4.0
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%fadd1 = fadd half %elt1, 2.0
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store volatile half %fmul0, half addrspace(1)* undef
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store volatile half %fadd1, half addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}v_extract_fneg_no_fold_v2f16:
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; GCN: {{flat|global}}_load_dword [[VAL:v[0-9]+]]
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; GCN: v_xor_b32_e32 [[NEG:v[0-9]+]], 0x80008000, [[VAL]]
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; CIVI: v_lshrrev_b32_e32 [[ELT1:v[0-9]+]], 16, [[NEG]]
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; GFX9: global_store_short_d16_hi v{{\[[0-9]+:[0-9]+\]}}, [[NEG]], off
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define amdgpu_kernel void @v_extract_fneg_no_fold_v2f16(<2 x half> addrspace(1)* %in) #0 {
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%val = load <2 x half>, <2 x half> addrspace(1)* %in
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%fneg = fsub <2 x half> <half -0.0, half -0.0>, %val
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%elt0 = extractelement <2 x half> %fneg, i32 0
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%elt1 = extractelement <2 x half> %fneg, i32 1
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store volatile half %elt0, half addrspace(1)* undef
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store volatile half %elt1, half addrspace(1)* undef
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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