Stephan Herhut 2c8afe1298 [mlir][gpu] Add support for f16 when lowering to nvvm intrinsics ... Summary: The NVVM target only provides implementations for tanh etc. on f32 and f64 operands. To also support f16, we now insert operations to extend to f32 and truncate back to f16 around the intrinsic call. Differential Revision: https://reviews.llvm.org/D81473		2020-06-09 19:33:45 +02:00
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CMakeLists.txt	[MLIR] Fix build when NVPTX is not enabled	2020-05-28 14:07:55 -07:00
ConvertKernelFuncToBlob.cpp	[mlir][gpu][mlir-cuda-runner] Refactor ConvertKernelFuncToCubin to be generic.	2020-05-28 09:08:28 -05:00
ConvertLaunchFuncToRuntimeCalls.cpp	[mlir] Change to re-enable cuda-runner tests	2020-06-06 09:31:51 -07:00
GPUOpsLowering.h	[mlir][GPUOpsLowering] Add missing include for FormatVariadic	2020-05-01 15:58:20 -07:00
IndexIntrinsicsOpLowering.h	[MLIR][LLVM] Make index type bitwidth configurable.	2020-03-27 12:42:54 +01:00
OpToFuncCallLowering.h	[mlir][gpu] Add support for f16 when lowering to nvvm intrinsics	2020-06-09 19:33:45 +02:00