llvm-project/llvm/test/CodeGen/MIR/AArch64
Matt Arsenault db78273b6e Add an ID field to StackObjects
On AMDGPU SGPR spills are really spilled to another register.
The spiller creates the spills to new frame index objects,
which is used as a placeholder.

This will eventually be replaced with a reference to a position
in a VGPR to write to and the frame index deleted. It is
most likely not a real stack location that can be shared
with another stack object.

This is a problem when StackSlotColoring decides it should
combine a frame index used for a normal VGPR spill with
a real stack location and a frame index used for an SGPR.

Add an ID field so that StackSlotColoring has a way
of knowing the different frame index types are
incompatible.

llvm-svn: 308673
2017-07-20 21:03:45 +00:00
..
atomic-memoperands.mir Enhance synchscope representation 2017-07-11 22:23:00 +00:00
cfi-def-cfa.mir MIRParser: Use shorter cfi identifiers 2016-07-26 18:20:00 +00:00
expected-target-flag-name.mir
generic-virtual-registers-error.mir CodeGen: Refactor MIR parsing 2017-06-06 00:44:35 +00:00
generic-virtual-registers-with-regbank-error.mir CodeGen: Refactor MIR parsing 2017-06-06 00:44:35 +00:00
intrinsics.mir CodeGen: add new "intrinsic" MachineOperand kind. 2016-07-29 20:32:59 +00:00
invalid-target-flag-name.mir
invalid-target-memoperands.mir [MIR] Add support for printing and parsing target MMO flags 2017-07-13 02:28:54 +00:00
lit.local.cfg
multiple-lhs-operands.mir
register-operand-bank.mir [Improve CodeGen Testing] This patch renables MIRPrinter print fields which have value equal to its default. 2017-06-06 08:16:19 +00:00
spill-fold.mir [AArch64] Fold some filled/spilled subreg COPYs 2017-01-05 21:51:42 +00:00
stack-object-local-offset.mir Add an ID field to StackObjects 2017-07-20 21:03:45 +00:00
target-flags.mir
target-memoperands.mir [AArch64][Falkor] Avoid HW prefetcher tag collisions (step 1) 2017-07-14 21:44:12 +00:00