llvm-project

History

Konstantin Zhuravlyov 5f5b586c99 AMDGPU: Handle non-temporal loads and stores Differential Revision: https://reviews.llvm.org/D36862 llvm-svn: 312729		2017-09-07 17:14:54 +00:00
..
AArch64	Add an ID field to StackObjects	2017-07-20 21:03:45 +00:00
AMDGPU	AMDGPU: Handle non-temporal loads and stores	2017-09-07 17:14:54 +00:00
ARM	[MIR] Print target-specific constant pools	2017-08-02 11:09:30 +00:00
Generic	[RegAllocFast] Add the proper initialize method to use the .mir infrastructure	2017-07-07 19:25:42 +00:00
Hexagon	[Hexagon] Handle Hexagon-specific machine operand target flags in MIR	2017-07-10 18:31:02 +00:00
Mips	MIRParser: Use shorter cfi identifiers	2016-07-26 18:20:00 +00:00
NVPTX	llc: Add support for -run-pass none	2016-07-16 02:24:59 +00:00
PowerPC	MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.	2016-08-24 01:32:41 +00:00
X86	[codeview] Generalize DIExpression parsing to handle load chains	2017-08-31 15:56:49 +00:00
README	Add README describing the intention of test/CodeGen/MIR	2016-12-09 20:16:12 +00:00

README

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.