llvm-project/llvm/test/MC/Disassembler
Peter Smith 14c1e98754 [ARM] Remove condition that could never be true
From Arm v8 Architecture Reference Manual F5.1.84 LDREXD
The ldrexd instruction in Arm state has the following conditions:

t = UInt(Rt); t2 = t + 1; n = UInt(Rn);
if Rt<0> == '1' || t2 == 15 || n == 15 then UNPREDICTABLE;

In when Rt is odd or if Rt is 14 (making t2 15).

In the implementation when the pair is the UNPREDICTABLE R14_R15 we
would ideally return SOFT_FAIL. We can't because there is no R14_R15
value for us to return so we fail early returning FAIL.

The early return for registers outside the bounds of the table means
the check for Rt == 14 (0xE) redundant which causes a static analyzer
to flag the condition as never being true.

To fix the warning I've removed the check and replaced with a comment
explaining the difference with the specification.

Fixes pr41660

Differential Revision: https://reviews.llvm.org/D77463
2020-04-07 09:50:56 +01:00
..
AArch64 [ARM] Add data gathering hint instruction 2020-04-05 15:21:00 +01:00
AMDGPU Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
ARC [lit] Delete empty lines at the end of lit.local.cfg NFC 2019-06-17 09:51:07 +00:00
ARM [ARM] Remove condition that could never be true 2020-04-07 09:50:56 +01:00
Hexagon [lit] Delete empty lines at the end of lit.local.cfg NFC 2019-06-17 09:51:07 +00:00
Lanai [lit] Delete empty lines at the end of lit.local.cfg NFC 2019-06-17 09:51:07 +00:00
MSP430 [lit] Delete empty lines at the end of lit.local.cfg NFC 2019-06-17 09:51:07 +00:00
Mips [mips] Implement Octeon+ `saa` and `saad` instructions 2019-11-07 13:58:50 +03:00
PowerPC [llvm] Fix missing FileCheck directive colons 2020-04-06 09:59:08 -06:00
RISCV [lit] Delete empty lines at the end of lit.local.cfg NFC 2019-06-17 09:51:07 +00:00
Sparc [lit] Delete empty lines at the end of lit.local.cfg NFC 2019-06-17 09:51:07 +00:00
SystemZ [SystemZ] Support z15 processor name 2019-09-20 23:04:45 +00:00
WebAssembly [WebAssembly] Allow multivalue types in block signature operands 2019-10-15 18:28:22 +00:00
X86 [X86] Add SERIALIZE instruction. 2020-04-02 16:19:23 +08:00
XCore