forked from OSchip/llvm-project
139 lines
4.7 KiB
TableGen
139 lines
4.7 KiB
TableGen
//===-- AMDGPUGIsel.td - AMDGPU GlobalISel Patterns---------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This files contains patterns that should only be used by GlobalISel. For
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// example patterns for V_* instructions that have S_* equivalents.
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// SelectionDAG does not support selecting V_* instructions.
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//===----------------------------------------------------------------------===//
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include "AMDGPU.td"
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def sd_vsrc0 : ComplexPattern<i32, 1, "">;
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def gi_vsrc0 :
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GIComplexOperandMatcher<s32, "selectVSRC0">,
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GIComplexPatternEquiv<sd_vsrc0>;
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def sd_vcsrc : ComplexPattern<i32, 1, "">;
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def gi_vcsrc :
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GIComplexOperandMatcher<s32, "selectVCSRC">,
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GIComplexPatternEquiv<sd_vcsrc>;
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def gi_vop3mods0 :
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GIComplexOperandMatcher<s32, "selectVOP3Mods0">,
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GIComplexPatternEquiv<VOP3Mods0>;
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def gi_vop3mods :
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GIComplexOperandMatcher<s32, "selectVOP3Mods">,
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GIComplexPatternEquiv<VOP3Mods>;
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def gi_vop3omods :
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GIComplexOperandMatcher<s32, "selectVOP3OMods">,
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GIComplexPatternEquiv<VOP3OMods>;
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class GISelSop2Pat <
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SDPatternOperator node,
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Instruction inst,
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ValueType dst_vt,
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ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat <
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(dst_vt (node (src0_vt SReg_32:$src0), (src1_vt SReg_32:$src1))),
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(inst src0_vt:$src0, src1_vt:$src1)
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>;
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class GISelVop2Pat <
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SDPatternOperator node,
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Instruction inst,
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ValueType dst_vt,
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ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat <
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(dst_vt (node (src0_vt (sd_vsrc0 src0_vt:$src0)), (src1_vt VGPR_32:$src1))),
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(inst src0_vt:$src0, src1_vt:$src1)
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>;
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class GISelVop2CommutePat <
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SDPatternOperator node,
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Instruction inst,
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ValueType dst_vt,
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ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat <
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(dst_vt (node (src1_vt VGPR_32:$src1), (src0_vt (sd_vsrc0 src0_vt:$src0)))),
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(inst src0_vt:$src0, src1_vt:$src1)
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>;
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class GISelVop3Pat2 <
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SDPatternOperator node,
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Instruction inst,
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ValueType dst_vt,
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ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat <
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(dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
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(inst src0_vt:$src0, src1_vt:$src1)
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>;
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class GISelVop3Pat2CommutePat <
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SDPatternOperator node,
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Instruction inst,
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ValueType dst_vt,
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ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat <
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(dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
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(inst src0_vt:$src1, src1_vt:$src0)
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>;
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class GISelVop3Pat2ModsPat <
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SDPatternOperator node,
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Instruction inst,
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ValueType dst_vt,
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ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat <
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(dst_vt (node (src0_vt (VOP3Mods0 src0_vt:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omods)),
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(src1_vt (VOP3Mods src1_vt:$src1, i32:$src1_modifiers)))),
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(inst i32:$src0_modifiers, src0_vt:$src0,
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i32:$src1_modifiers, src1_vt:$src1, $clamp, $omods)
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>;
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multiclass GISelVop2IntrPat <
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SDPatternOperator node, Instruction inst,
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ValueType dst_vt, ValueType src_vt = dst_vt> {
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def : GISelVop2Pat <node, inst, dst_vt, src_vt>;
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// FIXME: Intrinsics aren't marked as commutable, so we need to add an explcit
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// pattern to handle commuting. This is another reason why legalizing to a
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// generic machine instruction may be better that matching the intrinsic
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// directly.
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def : GISelVop2CommutePat <node, inst, dst_vt, src_vt>;
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}
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def : GISelSop2Pat <or, S_OR_B32, i32>;
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def : GISelVop2Pat <or, V_OR_B32_e32, i32>;
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def : GISelSop2Pat <sra, S_ASHR_I32, i32>;
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let AddedComplexity = 100 in {
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let SubtargetPredicate = isSICI in {
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def : GISelVop2Pat <sra, V_ASHR_I32_e32, i32>;
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}
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def : GISelVop2CommutePat <sra, V_ASHRREV_I32_e32, i32>;
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}
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def : GISelVop3Pat2CommutePat <sra, V_ASHRREV_I32_e64, i32>;
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// FIXME: Select directly to _e32 so we don't need to deal with modifiers.
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// FIXME: We can't re-use SelectionDAG patterns here because they match
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// against a custom SDNode and we would need to create a generic machine
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// instruction that is equivalent to the custom SDNode. This would also require
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// us to custom legalize the intrinsic to the new generic machine instruction,
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// but I can't get custom legalizing of intrinsic to work and I'm not sure if
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// this is even supported yet.
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defm : GISelVop2IntrPat <
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int_amdgcn_cvt_pkrtz, V_CVT_PKRTZ_F16_F32_e32, v2f16, f32>;
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defm : GISelVop2IntrPat <int_maxnum, V_MAX_F32_e32, f32>;
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def : GISelVop3Pat2ModsPat <int_maxnum, V_MAX_F64, f64>;
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defm : GISelVop2IntrPat <int_minnum, V_MIN_F32_e32, f32>;
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def : GISelVop3Pat2ModsPat <int_minnum, V_MIN_F64, f64>;
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