llvm-project/llvm/test/CodeGen
Craig Topper b2c65beb14 [X86] Rework the "sahf" feature flag to only apply to 64-bit mode.
SAHF/LAHF instructions are always available in 32-bit mode. Early
64-bit capable CPUs made the undefined opcodes in 64-bit mode. This
was changed on later CPUs.

We have a feature flag to control our usage of these instructions.
This feature flag is hooked up to a clang command line option
-msahf/-mno-sahf specifically to give control of the 64-bit mode
behavior.

In the backend X86Subtarget constructor we were explicitly forcing
+sahf into the feature flag string if we were not compiling for
64-bit mode. This was intended to make the predicates always allow
the instructions outside of 64-bit mode. Unfortunately, the way
it was placed into the string allowed -mno-sahf from clang to disable
SAHF instructions in 32-bit mode. This causes an assertion to fire
if you compile a floating point comparison with something like
"-march=pentium -mno-sahf" as our floating point comparison
handling on CPUs that don't support FCOMI/FUCOMI instructions
requires SAHF.

To fix this, this commit restricts the feature flag to only apply to
64-bit mode by ignoring the flag outside 64-bit mode in
X86Subtarget::hasLAHFSAHF(). This way we don't need to mess with
the feature string at all.
2020-07-22 16:57:46 -07:00
..
AArch64 [AArch64][SVE] Correctly allocate scavenging slot in presence of SVE. 2020-07-22 10:50:36 +01:00
AMDGPU AMDGPU/GlobalISel: Fix translation of indirect calls 2020-07-22 13:13:21 -04:00
ARC
ARM [Thumb] set code alignment for 16-bit load from constant pool 2020-07-22 10:12:41 +01:00
AVR [AVR] Rewrite the function calling convention. 2020-06-23 21:36:18 +12:00
BPF [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
Generic [llc] (almost) remove `--print-machineinstrs` 2020-07-20 10:43:28 -07:00
Hexagon [llc] (almost) remove `--print-machineinstrs` 2020-07-20 10:43:28 -07:00
Inputs
Lanai
MIR [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
MSP430 [MSP430] Declare comparison LibCalls as returning i16 instead of i32 2020-06-30 11:04:22 +03:00
Mips [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
NVPTX [NVPTX] Fix for NVPTX module asm regression 2020-06-24 11:17:09 -07:00
PowerPC [PowerPC][Power10] Fix vins*vlx instructions to have i32 arguments. 2020-07-22 17:58:14 -05:00
RISCV [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
SPARC [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
SystemZ [SystemZ] Simplify knownbits.ll test 2020-06-30 16:31:59 +02:00
Thumb
Thumb2 [ARM] Add predicated add reduction patterns 2020-07-22 17:30:02 +01:00
VE [VE] Support symbol with offset value 2020-07-01 23:55:27 +09:00
WebAssembly [WebAssembly] Autogenerate checks in simd-offset.ll 2020-07-22 10:12:26 -07:00
WinCFGuard
WinEH
X86 [X86] Rework the "sahf" feature flag to only apply to 64-bit mode. 2020-07-22 16:57:46 -07:00
XCore