llvm-project/llvm/test/MC/Disassembler
Oliver Stannard b25914e03f [AArch64] Add ARMv8.2-A FP16 scalar instructions
ARMv8.2-A adds 16-bit floating point versions of all existing VFP
floating-point instructions. This is an optional extension, so all of
these instructions require the FeatureFullFP16 subtarget feature.

Most of these instructions are the same as the 32- and 64-bit versions,
but with the type field (bits 23-22) set to 0b11. Previously the top bit
of the size field was always 0, so the instruction classes only provided
a 1-bit size field, which I have widened to 2 bits.

Differential Revision: http://reviews.llvm.org/D15014

llvm-svn: 254198
2015-11-27 13:04:48 +00:00
..
AArch64 [AArch64] Add ARMv8.2-A FP16 scalar instructions 2015-11-27 13:04:48 +00:00
ARM [ARM] Allow SP in rGPR, starting from ARMv8 2015-10-28 13:58:36 +00:00
Hexagon [Hexagon] Fixing store instructions and reenabling a few more tests. 2015-11-10 00:22:00 +00:00
Mips [mips][microMIPS] Implement MUL[_S].PH, MULEQ_S.W.PHL, MULEQ_S.W.PHR, MULEU_S.PH.QBL, MULEU_S.PH.QBR, MULQ_RS.PH, MULQ_RS.W, MULQ_S.PH and MULQ_S.W instructions 2015-11-20 07:14:52 +00:00
PowerPC [PowerPC] Replace cntlz[.] with cntlzw[.] 2015-10-28 03:26:45 +00:00
Sparc [Sparc] Implement i64 load/store support for 32-bit sparc. 2015-08-10 19:11:39 +00:00
SystemZ [SystemZ] Add assembly instructions for obtaining clock values as well as CPU features 2015-10-01 14:43:48 +00:00
X86 [llvm-mc] Ignore opcode size prefix in 64-bit CALL disassembly 2015-08-26 16:20:29 +00:00
XCore Reduce verbiage of lit.local.cfg files 2014-06-09 22:42:55 +00:00