forked from OSchip/llvm-project
158 lines
5.2 KiB
LLVM
158 lines
5.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux | FileCheck %s
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; RUN: llc < %s -mcpu=generic -mtriple=i686 -mattr=cmov | FileCheck %s --check-prefix=CHECK32
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declare i4 @llvm.uadd.sat.i4 (i4, i4)
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declare i32 @llvm.uadd.sat.i32 (i32, i32)
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declare i64 @llvm.uadd.sat.i64 (i64, i64)
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declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>)
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define i32 @func(i32 %x, i32 %y) {
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; CHECK-LABEL: func:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addl %esi, %edi
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: cmovael %edi, %eax
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; CHECK-NEXT: retq
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;
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; CHECK32-LABEL: func:
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; CHECK32: # %bb.0:
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK32-NEXT: addl {{[0-9]+}}(%esp), %ecx
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; CHECK32-NEXT: movl $-1, %eax
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; CHECK32-NEXT: cmovael %ecx, %eax
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; CHECK32-NEXT: retl
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%tmp = call i32 @llvm.uadd.sat.i32(i32 %x, i32 %y);
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ret i32 %tmp;
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}
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define i64 @func2(i64 %x, i64 %y) {
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; CHECK-LABEL: func2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addq %rsi, %rdi
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; CHECK-NEXT: movq $-1, %rax
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; CHECK-NEXT: cmovaeq %rdi, %rax
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; CHECK-NEXT: retq
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;
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; CHECK32-LABEL: func2:
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; CHECK32: # %bb.0:
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
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; CHECK32-NEXT: addl {{[0-9]+}}(%esp), %eax
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; CHECK32-NEXT: adcl {{[0-9]+}}(%esp), %edx
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; CHECK32-NEXT: movl $-1, %ecx
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; CHECK32-NEXT: cmovbl %ecx, %edx
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; CHECK32-NEXT: cmovbl %ecx, %eax
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; CHECK32-NEXT: retl
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%tmp = call i64 @llvm.uadd.sat.i64(i64 %x, i64 %y);
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ret i64 %tmp;
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}
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define i4 @func3(i4 %x, i4 %y) {
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; CHECK-LABEL: func3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: shlb $4, %sil
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; CHECK-NEXT: shlb $4, %dil
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; CHECK-NEXT: addb %sil, %dil
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; CHECK-NEXT: movb $-1, %al
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; CHECK-NEXT: jb .LBB2_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: .LBB2_2:
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; CHECK-NEXT: shrb $4, %al
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; CHECK-NEXT: retq
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;
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; CHECK32-LABEL: func3:
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; CHECK32: # %bb.0:
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; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %cl
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; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %al
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; CHECK32-NEXT: shlb $4, %al
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; CHECK32-NEXT: shlb $4, %cl
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; CHECK32-NEXT: addb %al, %cl
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; CHECK32-NEXT: movb $-1, %al
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; CHECK32-NEXT: jb .LBB2_2
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; CHECK32-NEXT: # %bb.1:
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; CHECK32-NEXT: movl %ecx, %eax
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; CHECK32-NEXT: .LBB2_2:
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; CHECK32-NEXT: shrb $4, %al
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; CHECK32-NEXT: retl
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%tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %y);
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ret i4 %tmp;
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}
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define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,1,2,3]
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; CHECK-NEXT: movd %xmm2, %eax
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; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,1,2,3]
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; CHECK-NEXT: movd %xmm2, %ecx
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; CHECK-NEXT: addl %eax, %ecx
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: cmovbl %eax, %ecx
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; CHECK-NEXT: movd %ecx, %xmm2
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; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1]
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; CHECK-NEXT: movd %xmm3, %ecx
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; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,0,1]
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; CHECK-NEXT: movd %xmm3, %edx
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; CHECK-NEXT: addl %ecx, %edx
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; CHECK-NEXT: cmovbl %eax, %edx
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; CHECK-NEXT: movd %edx, %xmm3
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; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
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; CHECK-NEXT: movd %xmm1, %ecx
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; CHECK-NEXT: movd %xmm0, %edx
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; CHECK-NEXT: addl %ecx, %edx
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; CHECK-NEXT: cmovbl %eax, %edx
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; CHECK-NEXT: movd %edx, %xmm2
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; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,2,3]
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; CHECK-NEXT: movd %xmm1, %ecx
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; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
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; CHECK-NEXT: movd %xmm0, %edx
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; CHECK-NEXT: addl %ecx, %edx
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; CHECK-NEXT: cmovbl %eax, %edx
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; CHECK-NEXT: movd %edx, %xmm0
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; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
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; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
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; CHECK-NEXT: movdqa %xmm2, %xmm0
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; CHECK-NEXT: retq
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;
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; CHECK32-LABEL: vec:
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; CHECK32: # %bb.0:
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; CHECK32-NEXT: pushl %ebx
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; CHECK32-NEXT: .cfi_def_cfa_offset 8
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; CHECK32-NEXT: pushl %edi
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; CHECK32-NEXT: .cfi_def_cfa_offset 12
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; CHECK32-NEXT: pushl %esi
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; CHECK32-NEXT: .cfi_def_cfa_offset 16
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; CHECK32-NEXT: .cfi_offset %esi, -16
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; CHECK32-NEXT: .cfi_offset %edi, -12
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; CHECK32-NEXT: .cfi_offset %ebx, -8
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edi
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; CHECK32-NEXT: addl {{[0-9]+}}(%esp), %edi
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; CHECK32-NEXT: movl $-1, %ebx
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; CHECK32-NEXT: cmovbl %ebx, %edi
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; CHECK32-NEXT: addl {{[0-9]+}}(%esp), %esi
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; CHECK32-NEXT: cmovbl %ebx, %esi
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; CHECK32-NEXT: addl {{[0-9]+}}(%esp), %edx
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; CHECK32-NEXT: cmovbl %ebx, %edx
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; CHECK32-NEXT: addl {{[0-9]+}}(%esp), %ecx
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; CHECK32-NEXT: cmovbl %ebx, %ecx
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; CHECK32-NEXT: movl %ecx, 12(%eax)
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; CHECK32-NEXT: movl %edx, 8(%eax)
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; CHECK32-NEXT: movl %esi, 4(%eax)
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; CHECK32-NEXT: movl %edi, (%eax)
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; CHECK32-NEXT: popl %esi
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; CHECK32-NEXT: .cfi_def_cfa_offset 12
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; CHECK32-NEXT: popl %edi
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; CHECK32-NEXT: .cfi_def_cfa_offset 8
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; CHECK32-NEXT: popl %ebx
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; CHECK32-NEXT: .cfi_def_cfa_offset 4
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; CHECK32-NEXT: retl $4
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%tmp = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y);
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ret <4 x i32> %tmp;
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}
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