llvm-project/llvm/lib/CodeGen
Reid Kleckner e092dad72c [codeview] Set the Nested and Scoped ClassOptions based on the scope chain
These are set on both the declaration record and the definition record.

llvm-svn: 274410
2016-07-02 00:11:07 +00:00
..
AsmPrinter [codeview] Set the Nested and Scoped ClassOptions based on the scope chain 2016-07-02 00:11:07 +00:00
GlobalISel [IRTranslator] Support the translation of or. 2016-06-10 20:50:35 +00:00
MIRParser [MIR] Check that generic virtual registers get a size. 2016-06-08 23:27:46 +00:00
SelectionDAG [CodeGen] Cleanup getVectorShuffle a bit to take advantage of its new ArrayRef argument and its begin/end iterators. Also use 'int' type for number of elements and loop iterators to remove several typecasts. No functional change intended. 2016-07-01 06:54:51 +00:00
AggressiveAntiDepBreaker.cpp Do not rename registers that do not start an independent live range 2016-05-26 18:22:53 +00:00
AggressiveAntiDepBreaker.h CodeGen: Use MachineInstr& in AntiDepBreaker API, NFC 2016-02-27 19:33:37 +00:00
AllocationOrder.cpp
AllocationOrder.h
Analysis.cpp Move shouldAssumeDSOLocal to Target. 2016-06-27 23:15:57 +00:00
AntiDepBreaker.h CodeGen: Use MachineInstr& in AntiDepBreaker API, NFC 2016-02-27 19:33:37 +00:00
AtomicExpandPass.cpp Support expanding partial-word cmpxchg to full-word cmpxchg in AtomicExpandPass. 2016-06-17 18:11:48 +00:00
BasicTargetTransformInfo.cpp constify the Function parameter to the TTI creation callback and 2015-09-16 23:38:13 +00:00
BranchFolding.cpp Codegen: Fix broken assumption in Tail Merge. 2016-06-24 18:16:36 +00:00
BranchFolding.h Reapply "[MBP] Reduce code size by running tail merging in MBP."" 2016-06-09 15:24:29 +00:00
BuiltinGCs.cpp [GC] Consolidate all built in GCs into a single file [NFC] 2016-01-19 03:57:18 +00:00
CMakeLists.txt StackColoring for SafeStack. 2016-06-29 20:37:43 +00:00
CalcSpillWeights.cpp CodeGen: Use MachineInstr& in TargetInstrInfo, NFC 2016-06-30 00:01:54 +00:00
CallingConvLower.cpp CodeGen: Factor out code for tail call result compatibility check; NFC 2016-03-30 22:46:04 +00:00
CodeGen.cpp [PM] Port PreISelIntrinsicLowering to the new PM 2016-06-24 20:13:42 +00:00
CodeGenPrepare.cpp Clarify that we match BSwap in InstCombine and BitReverse in CGP. NFC. 2016-05-25 16:22:14 +00:00
CriticalAntiDepBreaker.cpp [CodeGen] Fix problem with X86 byte registers in CriticalAntiDepBreaker 2016-05-26 23:08:52 +00:00
CriticalAntiDepBreaker.h [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
DFAPacketizer.cpp Apply clang-tidy's misc-static-assert where it makes sense. 2016-05-27 11:36:04 +00:00
DeadMachineInstructionElim.cpp Make DeadMachineInstructionElim preserve CFG 2016-06-21 23:01:17 +00:00
DetectDeadLanes.cpp Make DetectDeadLanes preserve CFG 2016-06-15 00:25:09 +00:00
DwarfEHPrepare.cpp Move EH-specific helper functions to a more appropriate place 2015-12-02 23:06:39 +00:00
EarlyIfConversion.cpp Add opt-bisect support to additional passes that can be skipped 2016-05-03 22:32:30 +00:00
EdgeBundles.cpp
ExecutionDepsFix.cpp CodeGen: Use MachineInstr& in TargetInstrInfo, NFC 2016-06-30 00:01:54 +00:00
ExpandISelPseudos.cpp CodeGen: Use MachineInstr& in ExpandISelPseudos, NFC 2016-06-30 23:09:39 +00:00
ExpandPostRAPseudos.cpp CodeGen: Use MachineInstr& in TargetInstrInfo, NFC 2016-06-30 00:01:54 +00:00
FaultMaps.cpp
FuncletLayout.cpp Introduce MachineFunctionProperties and the AllVRegsAllocated property 2016-03-28 17:05:30 +00:00
GCMetadata.cpp
GCMetadataPrinter.cpp Revert 258157 2016-01-19 18:41:10 +00:00
GCRootLowering.cpp Pass DebugLoc and SDLoc by const ref. 2016-06-12 15:39:02 +00:00
GCStrategy.cpp Revert 258157 2016-01-19 18:41:10 +00:00
GlobalMerge.cpp CodeGen: Make the global-merge pass independently testable, and add a test. 2016-05-19 04:38:56 +00:00
IfConversion.cpp CodeGen: Use MachineInstr& in IfConversion, NFC 2016-06-30 23:04:51 +00:00
ImplicitNullChecks.cpp CodeGen: Use MachineInstr& in TargetInstrInfo, NFC 2016-06-30 00:01:54 +00:00
InlineSpiller.cpp CodeGen: Use MachineInstr& in HoistSpillHelper, NFC 2016-06-30 23:28:15 +00:00
InterferenceCache.cpp CodeGen: Remove more ilist iterator implicit conversions, NFC 2015-10-09 19:13:58 +00:00
InterferenceCache.h
InterleavedAccessPass.cpp [ARM, AArch64] Match additional patterns to ldN instructions 2016-05-19 21:39:00 +00:00
IntrinsicLowering.cpp getParent() ^ 3 == getModule() ; NFCI 2015-12-14 17:24:23 +00:00
LLVMBuild.txt Include ProfileData as CodeGen's required library. 2016-02-22 22:54:14 +00:00
LLVMTargetMachine.cpp Delete MCCodeGenInfo. 2016-06-30 18:25:11 +00:00
LatencyPriorityQueue.cpp
LexicalScopes.cpp Fixed Dwarf debug info emission to skip DILexicalBlockFile entries. 2016-04-21 16:58:49 +00:00
LiveDebugValues.cpp Avoid duplicated map lookups. No functionality change intended. 2016-06-17 18:59:41 +00:00
LiveDebugVariables.cpp CodeGen: Use MachineInstr& in LDVImpl::handleDebugValue, NFC 2016-06-30 23:13:38 +00:00
LiveDebugVariables.h [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
LiveInterval.cpp CodeGen: Refactor renameDisconnectedComponents() as a pass 2016-05-31 22:38:06 +00:00
LiveIntervalAnalysis.cpp LiveIntervalAnalysis: findLastUseBefore() must ignore undef uses. 2016-06-11 00:31:28 +00:00
LiveIntervalUnion.cpp
LivePhysRegs.cpp livePhysRegs: Pass MBB by reference in addLive{Ins|Outs}(); NFC 2016-05-03 00:24:32 +00:00
LiveRangeCalc.cpp LiveIntervalAnalysis: Rework constructMainRangeFromSubranges() 2016-05-20 23:14:56 +00:00
LiveRangeCalc.h LiveIntervalAnalysis: Rework constructMainRangeFromSubranges() 2016-05-20 23:14:56 +00:00
LiveRangeEdit.cpp CodeGen: Use MachineInstr& in TargetInstrInfo, NFC 2016-06-30 00:01:54 +00:00
LiveRangeUtils.h CodeGen: Refactor renameDisconnectedComponents() as a pass 2016-05-31 22:38:06 +00:00
LiveRegMatrix.cpp TargetRegisterInfo: Introduce PrintLaneMask. 2015-09-25 21:51:24 +00:00
LiveStackAnalysis.cpp [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
LiveVariables.cpp CodeGen: Use MachineInstr& in LiveVariables API, NFC 2016-07-01 01:51:32 +00:00
LocalStackSlotAllocation.cpp CodeGen: Use MachineInstr& in LocalStackSlotAllocation, NFC 2016-06-30 23:39:46 +00:00
LowerEmuTLS.cpp Re-commit optimization bisect support (r267022) without new pass manager support. 2016-04-22 22:06:11 +00:00
MIRPrinter.cpp MIR: Support MachineMemOperands without associated value 2016-06-04 00:06:31 +00:00
MIRPrinter.h
MIRPrintingPass.cpp
MachineBasicBlock.cpp CodeGen: Use MachineInstr& in LiveVariables API, NFC 2016-07-01 01:51:32 +00:00
MachineBlockFrequencyInfo.cpp Fixed MSVC unresolved symbol error due to an incorrectly declared extern 2016-06-28 12:34:44 +00:00
MachineBlockPlacement.cpp [MBP] method interface cleanup 2016-07-01 05:46:48 +00:00
MachineBranchProbabilityInfo.cpp [MBP] add comments and bug fix 2016-06-15 03:03:30 +00:00
MachineCSE.cpp CodeGen: Use MachineInstr& in TargetInstrInfo, NFC 2016-06-30 00:01:54 +00:00
MachineCombiner.cpp [MachineCombiner] Support for floating-point FMA on ARM64 (re-commit r267098) 2016-04-24 05:14:01 +00:00
MachineCopyPropagation.cpp Make MachineCopyPropagation preserve CFG 2016-06-02 00:04:26 +00:00
MachineDominanceFrontier.cpp
MachineDominators.cpp [MDT] Always verify machine dominfo if expensive checking is enabled. 2016-06-24 17:15:04 +00:00
MachineFunction.cpp Pass DebugLoc and SDLoc by const ref. 2016-06-12 15:39:02 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp Improve error message reporting for MachineFunctionProperties 2016-04-21 22:19:24 +00:00
MachineFunctionPrinterPass.cpp Recommit r256952 "Filtering IR printing for print-after-all/print-before-all" 2016-01-06 22:55:03 +00:00
MachineInstr.cpp AMDGPU: Add convergent flag to INLINEASM instruction. 2016-06-22 18:51:08 +00:00
MachineInstrBundle.cpp Move instances of std::function. 2016-06-12 16:13:55 +00:00
MachineLICM.cpp CodeGen: Use MachineInstr& in TargetInstrInfo, NFC 2016-06-30 00:01:54 +00:00
MachineLoopInfo.cpp ADT: Remove == and != comparisons between ilist iterators and pointers 2016-02-21 20:39:50 +00:00
MachineModuleInfo.cpp Remove uses of builtin comma operator. 2016-02-18 22:09:30 +00:00
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachinePostDominators.cpp
MachineRegionInfo.cpp Introduce DominanceFrontierAnalysis to the new PassManager to compute DominanceFrontier. NFC 2016-02-25 17:54:15 +00:00
MachineRegisterInfo.cpp Replace MachineRegisterInfo::TracksLiveness with a MachineFunctionProperty 2016-04-11 23:32:13 +00:00
MachineSSAUpdater.cpp [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
MachineScheduler.cpp Target: Remove unused arguments from overrideSchedPolicy, NFC 2016-07-01 00:23:27 +00:00
MachineSink.cpp CodeGen: Use MachineInstr& in MachineSink, NFC 2016-07-01 00:11:48 +00:00
MachineTraceMetrics.cpp CodeGen: Use MachineInstr& more in MachineTraceMetrics, NFC 2016-07-01 00:05:40 +00:00
MachineVerifier.cpp CodeGen: Use MachineInstr& in TargetInstrInfo, NFC 2016-06-30 00:01:54 +00:00
OptimizePHIs.cpp Re-commit optimization bisect support (r267022) without new pass manager support. 2016-04-22 22:06:11 +00:00
PHIElimination.cpp CodeGen: Use MachineInstr& in LiveVariables API, NFC 2016-07-01 01:51:32 +00:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h
ParallelCG.cpp Apply another batch of fixes from clang-tidy's performance-unnecessary-value-param. 2016-06-17 20:41:14 +00:00
PatchableFunction.cpp Delete unused includes. NFC. 2016-06-30 12:19:16 +00:00
PeepholeOptimizer.cpp PeepholeOptimizer: Relax assert 2016-07-01 23:15:06 +00:00
PostRAHazardRecognizer.cpp CodeGen: Use MachineInstr& in PostRAHazardRecognizer, NFC 2016-07-01 00:50:29 +00:00
PostRASchedulerList.cpp CodeGen: Use MachineInstr& in PostRASchedulerList, NFC 2016-07-01 01:18:53 +00:00
PreISelIntrinsicLowering.cpp [PM] Port PreISelIntrinsicLowering to the new PM 2016-06-24 20:13:42 +00:00
ProcessImplicitDefs.cpp Revert "CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFC" 2016-02-22 20:49:58 +00:00
PrologEpilogInserter.cpp CodeGen: Use MachineInstr& in PrologEpilogInserter, NFC 2016-07-01 00:40:57 +00:00
PseudoSourceValue.cpp [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
README.txt
RegAllocBase.cpp [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
RegAllocBase.h Recommit r265547, and r265610,r265639,r265657 on top of it, plus 2016-04-13 03:08:27 +00:00
RegAllocBasic.cpp Recommit r265547, and r265610,r265639,r265657 on top of it, plus 2016-04-13 03:08:27 +00:00
RegAllocFast.cpp CodeGen: Use MachineInstr& in RegAllocFast, NFC 2016-07-01 15:03:37 +00:00
RegAllocGreedy.cpp Recommit r265547, and r265610,r265639,r265657 on top of it, plus 2016-04-13 03:08:27 +00:00
RegAllocPBQP.cpp Recommit r265547, and r265610,r265639,r265657 on top of it, plus 2016-04-13 03:08:27 +00:00
RegUsageInfoCollector.cpp Address a few coding style issues. NFC. 2016-06-15 21:14:02 +00:00
RegUsageInfoPropagate.cpp Interprocedural Register Allocation (IPRA): add a Transformation Pass 2016-06-10 18:37:21 +00:00
RegisterClassInfo.cpp
RegisterCoalescer.cpp CodeGen: Use MachineInstr& in RegisterCoalescer, NFC 2016-07-01 16:43:13 +00:00
RegisterCoalescer.h
RegisterPressure.cpp RegisterPressure: Fix default lanemask for missing regunit intervals 2016-04-29 02:44:54 +00:00
RegisterScavenging.cpp RegisterScavenging: Code cleanup; NFC 2016-06-30 00:23:54 +00:00
RegisterUsageInfo.cpp Interprocedural Register Allocation (IPRA) Analysis 2016-06-10 16:19:46 +00:00
RenameIndependentSubregs.cpp CodeGen: Refactor renameDisconnectedComponents() as a pass 2016-05-31 22:38:06 +00:00
SafeStack.cpp StackColoring for SafeStack. 2016-06-29 20:37:43 +00:00
SafeStackColoring.cpp StackColoring for SafeStack. 2016-06-29 20:37:43 +00:00
SafeStackColoring.h StackColoring for SafeStack. 2016-06-29 20:37:43 +00:00
SafeStackLayout.cpp StackColoring for SafeStack. 2016-06-29 20:37:43 +00:00
SafeStackLayout.h StackColoring for SafeStack. 2016-06-29 20:37:43 +00:00
ScheduleDAG.cpp MachineScheduler: Add regpressure information to debug dump 2015-11-06 20:59:02 +00:00
ScheduleDAGInstrs.cpp CodeGen: Use MachineInstr& in ScheduleDAGIntrs, NFC 2016-07-01 16:21:48 +00:00
ScheduleDAGPrinter.cpp [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
ScoreboardHazardRecognizer.cpp ScoreboardHazardRecognizer: unbreak TSAN by moving a static mutated variable to a member 2016-04-20 00:21:24 +00:00
ShadowStackGCLowering.cpp [GC] Consolidate all built in GCs into a single file [NFC] 2016-01-19 03:57:18 +00:00
ShrinkWrap.cpp [ShrinkWrapping] Give up on irreducible CFGs. 2016-01-07 01:23:49 +00:00
SjLjEHPrepare.cpp ADT: Remove == and != comparisons between ilist iterators and pointers 2016-02-21 20:39:50 +00:00
SlotIndexes.cpp CodeGen: Use MachineInstr& in SlotIndexes.cpp, NFC 2016-07-01 15:08:52 +00:00
SpillPlacement.cpp Reapply r263460: [SpillPlacement] Fix a quadratic behavior in spill placement. 2016-05-19 22:40:37 +00:00
SpillPlacement.h Reapply r263460: [SpillPlacement] Fix a quadratic behavior in spill placement. 2016-05-19 22:40:37 +00:00
Spiller.h Recommit r265547, and r265610,r265639,r265657 on top of it, plus 2016-04-13 03:08:27 +00:00
SplitKit.cpp InsertPointAnalysis: Move current live interval from being a class member 2016-05-23 19:39:19 +00:00
SplitKit.h InsertPointAnalysis: Move current live interval from being a class member 2016-05-23 19:39:19 +00:00
StackColoring.cpp Better fix for PR27903. 2016-06-01 17:55:10 +00:00
StackMapLivenessAnalysis.cpp livePhysRegs: Pass MBB by reference in addLive{Ins|Outs}(); NFC 2016-05-03 00:24:32 +00:00
StackMaps.cpp Fix a couple of redundant conditional expressions (PR27283, PR28282) 2016-04-11 20:35:01 +00:00
StackProtector.cpp Add an artificial line-0 debug location when the compiler emits a call to 2016-06-30 18:49:04 +00:00
StackSlotColoring.cpp CodeGen: Use MachineInstr& in TargetInstrInfo, NFC 2016-06-30 00:01:54 +00:00
TailDuplication.cpp Re-commit optimization bisect support (r267022) without new pass manager support. 2016-04-22 22:06:11 +00:00
TailDuplicator.cpp CodeGen: Use MachineInstr& in TargetInstrInfo, NFC 2016-06-30 00:01:54 +00:00
TargetFrameLoweringImpl.cpp CXX_FAST_TLS calling convention: performance improvement for PPC64 2016-04-08 12:04:32 +00:00
TargetInstrInfo.cpp TII: Fix inlineasm size counting comments as insts 2016-07-01 23:26:50 +00:00
TargetLoweringBase.cpp CodeGen: Use MachineInstr& in TargetLowering, NFC 2016-06-30 22:52:52 +00:00
TargetLoweringObjectFileImpl.cpp Add support for allowing us to create uniquely identified "COMDAT" or "ELF 2016-07-01 06:07:38 +00:00
TargetOptionsImpl.cpp
TargetPassConfig.cpp Interprocedural Register Allocation (IPRA): add a Transformation Pass 2016-06-10 18:37:21 +00:00
TargetRegisterInfo.cpp [TargetRegisterInfo] Re-apply r265734. 2016-04-08 00:51:00 +00:00
TargetSchedule.cpp CodeGen: Use MachineInstr& in TargetInstrInfo, NFC 2016-06-30 00:01:54 +00:00
TwoAddressInstructionPass.cpp CodeGen: Use MachineInstr& in LiveVariables API, NFC 2016-07-01 01:51:32 +00:00
UnreachableBlockElim.cpp CodeGen: Avoid iterator conversion in UnreachableBlockElim, NFC 2016-07-01 15:13:09 +00:00
VirtRegMap.cpp Use false for bool instead of 0 2016-06-02 18:37:21 +00:00
WinEHPrepare.cpp revert http://reviews.llvm.org/D21101 2016-06-30 17:52:24 +00:00

README.txt

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.