forked from OSchip/llvm-project
502 lines
16 KiB
LLVM
502 lines
16 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=sse2 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx < %s | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx512f < %s | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
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declare float @fminf(float, float)
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declare double @fmin(double, double)
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declare x86_fp80 @fminl(x86_fp80, x86_fp80)
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declare float @llvm.minnum.f32(float, float)
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declare double @llvm.minnum.f64(double, double)
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declare x86_fp80 @llvm.minnum.f80(x86_fp80, x86_fp80)
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declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>)
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declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>)
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declare <8 x float> @llvm.minnum.v8f32(<8 x float>, <8 x float>)
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declare <16 x float> @llvm.minnum.v16f32(<16 x float>, <16 x float>)
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declare <2 x double> @llvm.minnum.v2f64(<2 x double>, <2 x double>)
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declare <4 x double> @llvm.minnum.v4f64(<4 x double>, <4 x double>)
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declare <8 x double> @llvm.minnum.v8f64(<8 x double>, <8 x double>)
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; FIXME: As the vector tests show, the SSE run shouldn't need this many moves.
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define float @test_fminf(float %x, float %y) {
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; SSE-LABEL: test_fminf:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm0, %xmm2
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; SSE-NEXT: cmpunordss %xmm0, %xmm2
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; SSE-NEXT: movaps %xmm2, %xmm3
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; SSE-NEXT: andps %xmm1, %xmm3
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; SSE-NEXT: minss %xmm0, %xmm1
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; SSE-NEXT: andnps %xmm1, %xmm2
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; SSE-NEXT: orps %xmm3, %xmm2
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; SSE-NEXT: movaps %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test_fminf:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vminss %xmm0, %xmm1, %xmm2
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; AVX1-NEXT: vcmpunordss %xmm0, %xmm0, %xmm0
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; AVX1-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX512-LABEL: test_fminf:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vminss %xmm0, %xmm1, %xmm2
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; AVX512-NEXT: vcmpunordss %xmm0, %xmm0, %k1
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; AVX512-NEXT: vmovss %xmm1, %xmm0, %xmm2 {%k1}
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; AVX512-NEXT: vmovaps %xmm2, %xmm0
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; AVX512-NEXT: retq
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%z = call float @fminf(float %x, float %y) readnone
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ret float %z
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}
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define float @test_fminf_minsize(float %x, float %y) minsize {
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; CHECK-LABEL: test_fminf_minsize:
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; CHECK: # %bb.0:
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; CHECK-NEXT: jmp fminf # TAILCALL
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%z = call float @fminf(float %x, float %y) readnone
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ret float %z
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}
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; FIXME: As the vector tests show, the SSE run shouldn't need this many moves.
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define double @test_fmin(double %x, double %y) {
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; SSE-LABEL: test_fmin:
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; SSE: # %bb.0:
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; SSE-NEXT: movapd %xmm0, %xmm2
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; SSE-NEXT: cmpunordsd %xmm0, %xmm2
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; SSE-NEXT: movapd %xmm2, %xmm3
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; SSE-NEXT: andpd %xmm1, %xmm3
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; SSE-NEXT: minsd %xmm0, %xmm1
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; SSE-NEXT: andnpd %xmm1, %xmm2
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; SSE-NEXT: orpd %xmm3, %xmm2
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; SSE-NEXT: movapd %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test_fmin:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vminsd %xmm0, %xmm1, %xmm2
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; AVX1-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm0
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; AVX1-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX512-LABEL: test_fmin:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vminsd %xmm0, %xmm1, %xmm2
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; AVX512-NEXT: vcmpunordsd %xmm0, %xmm0, %k1
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; AVX512-NEXT: vmovsd %xmm1, %xmm0, %xmm2 {%k1}
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; AVX512-NEXT: vmovapd %xmm2, %xmm0
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; AVX512-NEXT: retq
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%z = call double @fmin(double %x, double %y) readnone
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ret double %z
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}
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define x86_fp80 @test_fminl(x86_fp80 %x, x86_fp80 %y) {
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; CHECK-LABEL: test_fminl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: subq $40, %rsp
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
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; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
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; CHECK-NEXT: fstpt {{[0-9]+}}(%rsp)
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; CHECK-NEXT: fstpt (%rsp)
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; CHECK-NEXT: callq fminl
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; CHECK-NEXT: addq $40, %rsp
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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%z = call x86_fp80 @fminl(x86_fp80 %x, x86_fp80 %y) readnone
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ret x86_fp80 %z
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}
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define float @test_intrinsic_fminf(float %x, float %y) {
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; SSE-LABEL: test_intrinsic_fminf:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm0, %xmm2
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; SSE-NEXT: cmpunordss %xmm0, %xmm2
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; SSE-NEXT: movaps %xmm2, %xmm3
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; SSE-NEXT: andps %xmm1, %xmm3
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; SSE-NEXT: minss %xmm0, %xmm1
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; SSE-NEXT: andnps %xmm1, %xmm2
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; SSE-NEXT: orps %xmm3, %xmm2
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; SSE-NEXT: movaps %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test_intrinsic_fminf:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vminss %xmm0, %xmm1, %xmm2
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; AVX1-NEXT: vcmpunordss %xmm0, %xmm0, %xmm0
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; AVX1-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX512-LABEL: test_intrinsic_fminf:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vminss %xmm0, %xmm1, %xmm2
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; AVX512-NEXT: vcmpunordss %xmm0, %xmm0, %k1
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; AVX512-NEXT: vmovss %xmm1, %xmm0, %xmm2 {%k1}
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; AVX512-NEXT: vmovaps %xmm2, %xmm0
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; AVX512-NEXT: retq
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%z = call float @llvm.minnum.f32(float %x, float %y) readnone
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ret float %z
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}
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define double @test_intrinsic_fmin(double %x, double %y) {
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; SSE-LABEL: test_intrinsic_fmin:
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; SSE: # %bb.0:
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; SSE-NEXT: movapd %xmm0, %xmm2
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; SSE-NEXT: cmpunordsd %xmm0, %xmm2
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; SSE-NEXT: movapd %xmm2, %xmm3
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; SSE-NEXT: andpd %xmm1, %xmm3
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; SSE-NEXT: minsd %xmm0, %xmm1
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; SSE-NEXT: andnpd %xmm1, %xmm2
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; SSE-NEXT: orpd %xmm3, %xmm2
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; SSE-NEXT: movapd %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test_intrinsic_fmin:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vminsd %xmm0, %xmm1, %xmm2
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; AVX1-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm0
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; AVX1-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX512-LABEL: test_intrinsic_fmin:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vminsd %xmm0, %xmm1, %xmm2
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; AVX512-NEXT: vcmpunordsd %xmm0, %xmm0, %k1
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; AVX512-NEXT: vmovsd %xmm1, %xmm0, %xmm2 {%k1}
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; AVX512-NEXT: vmovapd %xmm2, %xmm0
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; AVX512-NEXT: retq
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%z = call double @llvm.minnum.f64(double %x, double %y) readnone
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ret double %z
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}
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define x86_fp80 @test_intrinsic_fminl(x86_fp80 %x, x86_fp80 %y) {
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; CHECK-LABEL: test_intrinsic_fminl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: subq $40, %rsp
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
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; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
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; CHECK-NEXT: fstpt {{[0-9]+}}(%rsp)
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; CHECK-NEXT: fstpt (%rsp)
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; CHECK-NEXT: callq fminl
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; CHECK-NEXT: addq $40, %rsp
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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%z = call x86_fp80 @llvm.minnum.f80(x86_fp80 %x, x86_fp80 %y) readnone
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ret x86_fp80 %z
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}
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define <2 x float> @test_intrinsic_fmin_v2f32(<2 x float> %x, <2 x float> %y) {
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; SSE-LABEL: test_intrinsic_fmin_v2f32:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm1, %xmm2
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; SSE-NEXT: minps %xmm0, %xmm2
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; SSE-NEXT: cmpunordps %xmm0, %xmm0
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; SSE-NEXT: andps %xmm0, %xmm1
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; SSE-NEXT: andnps %xmm2, %xmm0
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; SSE-NEXT: orps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_intrinsic_fmin_v2f32:
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; AVX: # %bb.0:
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; AVX-NEXT: vminps %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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%z = call <2 x float> @llvm.minnum.v2f32(<2 x float> %x, <2 x float> %y) readnone
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ret <2 x float> %z
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}
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define <4 x float> @test_intrinsic_fmin_v4f32(<4 x float> %x, <4 x float> %y) {
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; SSE-LABEL: test_intrinsic_fmin_v4f32:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm1, %xmm2
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; SSE-NEXT: minps %xmm0, %xmm2
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; SSE-NEXT: cmpunordps %xmm0, %xmm0
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; SSE-NEXT: andps %xmm0, %xmm1
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; SSE-NEXT: andnps %xmm2, %xmm0
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; SSE-NEXT: orps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_intrinsic_fmin_v4f32:
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; AVX: # %bb.0:
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; AVX-NEXT: vminps %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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%z = call <4 x float> @llvm.minnum.v4f32(<4 x float> %x, <4 x float> %y) readnone
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ret <4 x float> %z
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}
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define <8 x float> @test_intrinsic_fmin_v8f32(<8 x float> %x, <8 x float> %y) {
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; SSE-LABEL: test_intrinsic_fmin_v8f32:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm2, %xmm4
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; SSE-NEXT: minps %xmm0, %xmm4
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; SSE-NEXT: cmpunordps %xmm0, %xmm0
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; SSE-NEXT: andps %xmm0, %xmm2
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; SSE-NEXT: andnps %xmm4, %xmm0
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; SSE-NEXT: orps %xmm2, %xmm0
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; SSE-NEXT: movaps %xmm3, %xmm2
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; SSE-NEXT: minps %xmm1, %xmm2
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; SSE-NEXT: cmpunordps %xmm1, %xmm1
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; SSE-NEXT: andps %xmm1, %xmm3
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; SSE-NEXT: andnps %xmm2, %xmm1
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; SSE-NEXT: orps %xmm3, %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_intrinsic_fmin_v8f32:
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; AVX: # %bb.0:
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; AVX-NEXT: vminps %ymm0, %ymm1, %ymm2
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; AVX-NEXT: vcmpunordps %ymm0, %ymm0, %ymm0
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; AVX-NEXT: vblendvps %ymm0, %ymm1, %ymm2, %ymm0
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; AVX-NEXT: retq
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%z = call <8 x float> @llvm.minnum.v8f32(<8 x float> %x, <8 x float> %y) readnone
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ret <8 x float> %z
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}
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define <16 x float> @test_intrinsic_fmin_v16f32(<16 x float> %x, <16 x float> %y) {
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; SSE-LABEL: test_intrinsic_fmin_v16f32:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm4, %xmm8
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; SSE-NEXT: minps %xmm0, %xmm8
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; SSE-NEXT: cmpunordps %xmm0, %xmm0
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; SSE-NEXT: andps %xmm0, %xmm4
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; SSE-NEXT: andnps %xmm8, %xmm0
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; SSE-NEXT: orps %xmm4, %xmm0
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; SSE-NEXT: movaps %xmm5, %xmm4
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; SSE-NEXT: minps %xmm1, %xmm4
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; SSE-NEXT: cmpunordps %xmm1, %xmm1
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; SSE-NEXT: andps %xmm1, %xmm5
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; SSE-NEXT: andnps %xmm4, %xmm1
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; SSE-NEXT: orps %xmm5, %xmm1
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; SSE-NEXT: movaps %xmm6, %xmm4
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; SSE-NEXT: minps %xmm2, %xmm4
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; SSE-NEXT: cmpunordps %xmm2, %xmm2
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; SSE-NEXT: andps %xmm2, %xmm6
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; SSE-NEXT: andnps %xmm4, %xmm2
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; SSE-NEXT: orps %xmm6, %xmm2
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; SSE-NEXT: movaps %xmm7, %xmm4
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; SSE-NEXT: minps %xmm3, %xmm4
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; SSE-NEXT: cmpunordps %xmm3, %xmm3
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; SSE-NEXT: andps %xmm3, %xmm7
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; SSE-NEXT: andnps %xmm4, %xmm3
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; SSE-NEXT: orps %xmm7, %xmm3
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test_intrinsic_fmin_v16f32:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vminps %ymm0, %ymm2, %ymm4
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; AVX1-NEXT: vcmpunordps %ymm0, %ymm0, %ymm0
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; AVX1-NEXT: vblendvps %ymm0, %ymm2, %ymm4, %ymm0
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; AVX1-NEXT: vminps %ymm1, %ymm3, %ymm2
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; AVX1-NEXT: vcmpunordps %ymm1, %ymm1, %ymm1
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; AVX1-NEXT: vblendvps %ymm1, %ymm3, %ymm2, %ymm1
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; AVX1-NEXT: retq
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;
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; AVX512-LABEL: test_intrinsic_fmin_v16f32:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vminps %zmm0, %zmm1, %zmm2
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; AVX512-NEXT: vcmpunordps %zmm0, %zmm0, %k1
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; AVX512-NEXT: vmovaps %zmm1, %zmm2 {%k1}
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; AVX512-NEXT: vmovaps %zmm2, %zmm0
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; AVX512-NEXT: retq
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%z = call <16 x float> @llvm.minnum.v16f32(<16 x float> %x, <16 x float> %y) readnone
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ret <16 x float> %z
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}
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define <2 x double> @test_intrinsic_fmin_v2f64(<2 x double> %x, <2 x double> %y) {
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; SSE-LABEL: test_intrinsic_fmin_v2f64:
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; SSE: # %bb.0:
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; SSE-NEXT: movapd %xmm1, %xmm2
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; SSE-NEXT: minpd %xmm0, %xmm2
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; SSE-NEXT: cmpunordpd %xmm0, %xmm0
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; SSE-NEXT: andpd %xmm0, %xmm1
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; SSE-NEXT: andnpd %xmm2, %xmm0
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; SSE-NEXT: orpd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_intrinsic_fmin_v2f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vminpd %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordpd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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%z = call <2 x double> @llvm.minnum.v2f64(<2 x double> %x, <2 x double> %y) readnone
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ret <2 x double> %z
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}
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define <4 x double> @test_intrinsic_fmin_v4f64(<4 x double> %x, <4 x double> %y) {
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; SSE-LABEL: test_intrinsic_fmin_v4f64:
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; SSE: # %bb.0:
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; SSE-NEXT: movapd %xmm2, %xmm4
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; SSE-NEXT: minpd %xmm0, %xmm4
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; SSE-NEXT: cmpunordpd %xmm0, %xmm0
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; SSE-NEXT: andpd %xmm0, %xmm2
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; SSE-NEXT: andnpd %xmm4, %xmm0
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; SSE-NEXT: orpd %xmm2, %xmm0
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; SSE-NEXT: movapd %xmm3, %xmm2
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; SSE-NEXT: minpd %xmm1, %xmm2
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; SSE-NEXT: cmpunordpd %xmm1, %xmm1
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; SSE-NEXT: andpd %xmm1, %xmm3
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; SSE-NEXT: andnpd %xmm2, %xmm1
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; SSE-NEXT: orpd %xmm3, %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_intrinsic_fmin_v4f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vminpd %ymm0, %ymm1, %ymm2
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; AVX-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm0
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; AVX-NEXT: vblendvpd %ymm0, %ymm1, %ymm2, %ymm0
|
|
; AVX-NEXT: retq
|
|
%z = call <4 x double> @llvm.minnum.v4f64(<4 x double> %x, <4 x double> %y) readnone
|
|
ret <4 x double> %z
|
|
}
|
|
|
|
define <8 x double> @test_intrinsic_fmin_v8f64(<8 x double> %x, <8 x double> %y) {
|
|
; SSE-LABEL: test_intrinsic_fmin_v8f64:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: movapd %xmm4, %xmm8
|
|
; SSE-NEXT: minpd %xmm0, %xmm8
|
|
; SSE-NEXT: cmpunordpd %xmm0, %xmm0
|
|
; SSE-NEXT: andpd %xmm0, %xmm4
|
|
; SSE-NEXT: andnpd %xmm8, %xmm0
|
|
; SSE-NEXT: orpd %xmm4, %xmm0
|
|
; SSE-NEXT: movapd %xmm5, %xmm4
|
|
; SSE-NEXT: minpd %xmm1, %xmm4
|
|
; SSE-NEXT: cmpunordpd %xmm1, %xmm1
|
|
; SSE-NEXT: andpd %xmm1, %xmm5
|
|
; SSE-NEXT: andnpd %xmm4, %xmm1
|
|
; SSE-NEXT: orpd %xmm5, %xmm1
|
|
; SSE-NEXT: movapd %xmm6, %xmm4
|
|
; SSE-NEXT: minpd %xmm2, %xmm4
|
|
; SSE-NEXT: cmpunordpd %xmm2, %xmm2
|
|
; SSE-NEXT: andpd %xmm2, %xmm6
|
|
; SSE-NEXT: andnpd %xmm4, %xmm2
|
|
; SSE-NEXT: orpd %xmm6, %xmm2
|
|
; SSE-NEXT: movapd %xmm7, %xmm4
|
|
; SSE-NEXT: minpd %xmm3, %xmm4
|
|
; SSE-NEXT: cmpunordpd %xmm3, %xmm3
|
|
; SSE-NEXT: andpd %xmm3, %xmm7
|
|
; SSE-NEXT: andnpd %xmm4, %xmm3
|
|
; SSE-NEXT: orpd %xmm7, %xmm3
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX1-LABEL: test_intrinsic_fmin_v8f64:
|
|
; AVX1: # %bb.0:
|
|
; AVX1-NEXT: vminpd %ymm0, %ymm2, %ymm4
|
|
; AVX1-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm0
|
|
; AVX1-NEXT: vblendvpd %ymm0, %ymm2, %ymm4, %ymm0
|
|
; AVX1-NEXT: vminpd %ymm1, %ymm3, %ymm2
|
|
; AVX1-NEXT: vcmpunordpd %ymm1, %ymm1, %ymm1
|
|
; AVX1-NEXT: vblendvpd %ymm1, %ymm3, %ymm2, %ymm1
|
|
; AVX1-NEXT: retq
|
|
;
|
|
; AVX512-LABEL: test_intrinsic_fmin_v8f64:
|
|
; AVX512: # %bb.0:
|
|
; AVX512-NEXT: vminpd %zmm0, %zmm1, %zmm2
|
|
; AVX512-NEXT: vcmpunordpd %zmm0, %zmm0, %k1
|
|
; AVX512-NEXT: vmovapd %zmm1, %zmm2 {%k1}
|
|
; AVX512-NEXT: vmovapd %zmm2, %zmm0
|
|
; AVX512-NEXT: retq
|
|
%z = call <8 x double> @llvm.minnum.v8f64(<8 x double> %x, <8 x double> %y) readnone
|
|
ret <8 x double> %z
|
|
}
|
|
|
|
; The IR-level FMF propagate to the node. With nnan, there's no need to blend.
|
|
|
|
define float @minnum_intrinsic_nnan_fmf_f32(float %a, float %b) {
|
|
; SSE-LABEL: minnum_intrinsic_nnan_fmf_f32:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: minss %xmm1, %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: minnum_intrinsic_nnan_fmf_f32:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vminss %xmm1, %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%r = tail call nnan float @llvm.minnum.f32(float %a, float %b)
|
|
ret float %r
|
|
}
|
|
|
|
; Make sure vectors work too.
|
|
|
|
define <2 x double> @minnum_intrinsic_nnan_fmf_v2f64(<2 x double> %a, <2 x double> %b) {
|
|
; SSE-LABEL: minnum_intrinsic_nnan_fmf_v2f64:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: minpd %xmm1, %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: minnum_intrinsic_nnan_fmf_v2f64:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vminpd %xmm1, %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%r = tail call nnan <2 x double> @llvm.minnum.v2f64(<2 x double> %a, <2 x double> %b)
|
|
ret <2 x double> %r
|
|
}
|
|
|
|
; Current (but legacy someday): a function-level attribute should also enable the fold.
|
|
|
|
define double @minnum_intrinsic_nnan_attr_f64(double %a, double %b) #0 {
|
|
; SSE-LABEL: minnum_intrinsic_nnan_attr_f64:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: minsd %xmm1, %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: minnum_intrinsic_nnan_attr_f64:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vminsd %xmm1, %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%r = tail call double @llvm.minnum.f64(double %a, double %b)
|
|
ret double %r
|
|
}
|
|
|
|
; Make sure vectors work too.
|
|
|
|
define <4 x float> @minnum_intrinsic_nnan_attr_v4f32(<4 x float> %a, <4 x float> %b) #0 {
|
|
; SSE-LABEL: minnum_intrinsic_nnan_attr_v4f32:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: minps %xmm1, %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: minnum_intrinsic_nnan_attr_v4f32:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vminps %xmm1, %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%r = tail call <4 x float> @llvm.minnum.v4f32(<4 x float> %a, <4 x float> %b)
|
|
ret <4 x float> %r
|
|
}
|
|
|
|
define float @test_minnum_const_op1(float %x) {
|
|
; SSE-LABEL: test_minnum_const_op1:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: minss {{.*}}(%rip), %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: test_minnum_const_op1:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vminss {{.*}}(%rip), %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%r = call float @llvm.minnum.f32(float 1.0, float %x)
|
|
ret float %r
|
|
}
|
|
|
|
define float @test_minnum_const_op2(float %x) {
|
|
; SSE-LABEL: test_minnum_const_op2:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: minss {{.*}}(%rip), %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: test_minnum_const_op2:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vminss {{.*}}(%rip), %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%r = call float @llvm.minnum.f32(float %x, float 1.0)
|
|
ret float %r
|
|
}
|
|
|
|
attributes #0 = { "no-nans-fp-math"="true" }
|
|
|