forked from OSchip/llvm-project
135 lines
6.1 KiB
TableGen
135 lines
6.1 KiB
TableGen
//=- MicroMips64r6InstrInfo.td - Instruction Information -*- tablegen -*- -=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes MicroMips64r6 instructions.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//
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// Instruction Encodings
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//
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//===----------------------------------------------------------------------===//
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class DAUI_MMR6_ENC : DAUI_FM_MMR6;
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class DAHI_MMR6_ENC : POOL32I_ADD_IMM_FM_MMR6<0b10001>;
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class DATI_MMR6_ENC : POOL32I_ADD_IMM_FM_MMR6<0b10000>;
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class DEXT_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b101100>;
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class DEXTM_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b100100>;
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class DEXTU_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b010100>;
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class DALIGN_MMR6_ENC : POOL32S_DALIGN_FM_MMR6;
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class DDIV_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddiv", 0b100011000>;
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class DMOD_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmod", 0b101011000>;
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class DDIVU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddivu", 0b110011000>;
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class DMODU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmodu", 0b111011000>;
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class DINSU_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b110100>;
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class DINSM_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b000100>;
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class DINS_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b001100>;
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//===----------------------------------------------------------------------===//
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//
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// Instruction Descriptions
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//
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//===----------------------------------------------------------------------===//
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class DAUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
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: MMR6Arch<instr_asm>, MipsR6Inst {
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dag OutOperandList = (outs GPROpnd:$rt);
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dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
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string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
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list<dag> Pattern = [];
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}
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class DAUI_MMR6_DESC : DAUI_MMR6_DESC_BASE<"daui", GPR64Opnd>;
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class DAHI_DATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
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: MMR6Arch<instr_asm>, MipsR6Inst {
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dag OutOperandList = (outs GPROpnd:$rs);
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dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
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string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
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string Constraints = "$rs = $rt";
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}
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class DAHI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dahi", GPR64Opnd>;
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class DATI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dati", GPR64Opnd>;
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class EXTBITS_DESC_BASE<string instr_asm, RegisterOperand RO, Operand PosOpnd,
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Operand SizeOpnd, SDPatternOperator Op = null_frag>
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: MMR6Arch<instr_asm>, MipsR6Inst {
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dag OutOperandList = (outs RO:$rt);
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dag InOperandList = (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size);
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string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $pos, $size");
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list<dag> Pattern = [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))];
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InstrItinClass Itinerary = II_EXT;
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Format Form = FrmR;
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string BaseOpcode = instr_asm;
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}
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// TODO: Add 'pos + size' constraint check to dext* instructions
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// DEXT: 0 < pos + size <= 63
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// DEXTM, DEXTU: 32 < pos + size <= 64
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class DEXT_MMR6_DESC : EXTBITS_DESC_BASE<"dext", GPR64Opnd, uimm5_report_uimm6,
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uimm5_plus1, MipsExt>;
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class DEXTM_MMR6_DESC : EXTBITS_DESC_BASE<"dextm", GPR64Opnd, uimm5,
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uimm5_plus33, MipsExt>;
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class DEXTU_MMR6_DESC : EXTBITS_DESC_BASE<"dextu", GPR64Opnd, uimm5_plus32,
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uimm5_plus1, MipsExt>;
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class DALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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Operand ImmOpnd> : MMR6Arch<instr_asm>, MipsR6Inst {
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dag OutOperandList = (outs GPROpnd:$rd);
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dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
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string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
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list<dag> Pattern = [];
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}
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class DALIGN_MMR6_DESC : DALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>;
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class DDIV_MM64R6_DESC : ArithLogicR<"ddiv", GPR32Opnd>;
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class DMOD_MM64R6_DESC : ArithLogicR<"dmod", GPR32Opnd>;
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class DDIVU_MM64R6_DESC : ArithLogicR<"ddivu", GPR32Opnd>;
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class DMODU_MM64R6_DESC : ArithLogicR<"dmodu", GPR32Opnd>;
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class DINSU_MM64R6_DESC : InsBase<"dinsu", GPR64Opnd, uimm5_plus32,
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uimm5_inssize_plus1, MipsIns>;
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class DINSM_MM64R6_DESC : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64>;
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class DINS_MM64R6_DESC : InsBase<"dins", GPR64Opnd, uimm5, uimm5_inssize_plus1,
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MipsIns>;
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//===----------------------------------------------------------------------===//
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//
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// Instruction Definitions
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//
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//===----------------------------------------------------------------------===//
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let DecoderNamespace = "MicroMipsR6" in {
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def DAUI_MM64R6 : StdMMR6Rel, DAUI_MMR6_DESC, DAUI_MMR6_ENC, ISA_MICROMIPS64R6;
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def DAHI_MM64R6 : StdMMR6Rel, DAHI_MMR6_DESC, DAHI_MMR6_ENC, ISA_MICROMIPS64R6;
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def DATI_MM64R6 : StdMMR6Rel, DATI_MMR6_DESC, DATI_MMR6_ENC, ISA_MICROMIPS64R6;
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def DEXT_MM64R6 : StdMMR6Rel, DEXT_MMR6_DESC, DEXT_MMR6_ENC,
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ISA_MICROMIPS64R6;
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def DEXTM_MM64R6 : StdMMR6Rel, DEXTM_MMR6_DESC, DEXTM_MMR6_ENC,
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ISA_MICROMIPS64R6;
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def DEXTU_MM64R6 : StdMMR6Rel, DEXTU_MMR6_DESC, DEXTU_MMR6_ENC,
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ISA_MICROMIPS64R6;
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def DALIGN_MM64R6 : StdMMR6Rel, DALIGN_MMR6_DESC, DALIGN_MMR6_ENC,
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ISA_MICROMIPS64R6;
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def DDIV_MM64R6 : R6MMR6Rel, DDIV_MM64R6_DESC, DDIV_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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def DMOD_MM64R6 : R6MMR6Rel, DMOD_MM64R6_DESC, DMOD_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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def DDIVU_MM64R6 : R6MMR6Rel, DDIVU_MM64R6_DESC, DDIVU_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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def DMODU_MM64R6 : R6MMR6Rel, DMODU_MM64R6_DESC, DMODU_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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def DINSU_MM64R6: R6MMR6Rel, DINSU_MM64R6_DESC, DINSU_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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def DINSM_MM64R6: R6MMR6Rel, DINSM_MM64R6_DESC, DINSM_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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def DINS_MM64R6: R6MMR6Rel, DINS_MM64R6_DESC, DINS_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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}
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