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llvm-project/llvm/test/CodeGen
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Carl Ritson f898edd117 [AMDGPU] Prevent sequences of non-instructions disrupting GCNHazardRecognizer wait state counting 
Summary:
This fixes a bug where a large number of implicit def instructions can fill the GCNHazardRecognizer lookahead buffer causing required NOPs to not be inserted.

Reviewers: nhaehnle, arsenm

Reviewed By: arsenm

Subscribers: sheredom, kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D51726

Change-Id: Ie75338f94de704ee5816b05afd0c922c6748a95b
llvm-svn: 341798
 		2018-09-10 10:14:48 +00:00
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AArch64 [AArch64] Support reserving x1-7 registers. 2018-09-07 20:58:57 +00:00
AMDGPU [AMDGPU] Prevent sequences of non-instructions disrupting GCNHazardRecognizer wait state counting 2018-09-10 10:14:48 +00:00
ARC
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ARM ARM: fix Thumb2 CodeGen for ldrex with folded frame-index. 2018-09-07 09:21:25 +00:00
AVR [AVR] Redefine the 'LSL' instruction as an alias of 'ADD' 2018-09-01 12:23:00 +00:00
BPF bpf: add missing RegState to notify MachineInstr verifier necessary register usage 2018-07-27 16:58:52 +00:00
Generic [DWARF] Unclamp line table version on Darwin for v5 and later. 2018-08-08 21:16:50 +00:00
Hexagon Add support for getRegisterByName. 2018-09-07 13:36:21 +00:00
Inputs
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Lanai
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MIR AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
MSP430 [DAGCombiner] Add X / X -> 1 & X % X -> 0 folds (test tweaks) 2018-08-29 11:18:14 +00:00
Mips [mips] Disable the selection of mixed microMIPS/MIPS code 2018-09-03 20:48:55 +00:00
NVPTX [NVPTX] Implement isLegalToVectorizeLoadChain 2018-08-27 17:29:43 +00:00
Nios2
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PowerPC [PowerPC] Combine ADD to ADDZE 2018-09-07 07:56:05 +00:00
RISCV [RISCV] atomic_store_nn have a different layout to regular store 2018-08-27 07:08:18 +00:00
SPARC [Sparc] Use ANDN instead of AND if constant can be encoded more efficiently 2018-08-30 14:05:26 +00:00
SystemZ [DAGCombiner] Add X / X -> 1 & X % X -> 0 folds (test tweaks) 2018-08-29 11:18:14 +00:00
Thumb CodeGen: Make computeRegisterLiveness search forward first 2018-08-30 07:18:10 +00:00
Thumb2 [SelectionDAG] Improve the legalisation lowering of UMULO. 2018-08-16 18:39:39 +00:00
WebAssembly [WebAssembly] v8x16.shuffle 2018-09-07 21:54:46 +00:00
WinCFGuard Rename the cfguard module flag to cfguardtable 2018-08-10 09:48:53 +00:00
WinEH
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X86 [X86] Custom type legalize (v2i32 (fp_to_uint v2f64))) without avx512vl by widening to v4i32 and v4f64 instead of v8i32 and v8f64. Make it aware of x86-experimental-vector-widening-legalization 2018-09-09 20:36:36 +00:00
XCore [DAGCombiner] extend(ifpositive(X)) -> shift-right (not X) 2018-07-15 16:27:07 +00:00