forked from OSchip/llvm-project
326 lines
11 KiB
LLVM
326 lines
11 KiB
LLVM
; check AVX2 instructions that are disabled in case avx512VL/avx512BW present
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -show-mc-encoding -mcpu=core-avx2 -mattr=+avx2 -o /dev/null
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -show-mc-encoding -mcpu=knl -o /dev/null
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -show-mc-encoding -mcpu=knl -mattr=+avx512vl -o /dev/null
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -show-mc-encoding -mcpu=knl -mattr=+avx512bw -o /dev/null
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -show-mc-encoding -mcpu=knl -mattr=+avx512vl -mattr=+avx512bw -o /dev/null
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -show-mc-encoding -mcpu=skx -o /dev/null
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define <4 x i64> @vpand_256(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
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; Force the execution domain with an add.
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%a2 = add <4 x i64> %a, <i64 1, i64 1, i64 1, i64 1>
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%x = and <4 x i64> %a2, %b
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ret <4 x i64> %x
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}
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define <2 x i64> @vpand_128(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
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; Force the execution domain with an add.
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%a2 = add <2 x i64> %a, <i64 1, i64 1>
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%x = and <2 x i64> %a2, %b
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ret <2 x i64> %x
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}
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define <4 x i64> @vpandn_256(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
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; Force the execution domain with an add.
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%a2 = add <4 x i64> %a, <i64 1, i64 1, i64 1, i64 1>
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%y = xor <4 x i64> %a2, <i64 -1, i64 -1, i64 -1, i64 -1>
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%x = and <4 x i64> %a, %y
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ret <4 x i64> %x
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}
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define <2 x i64> @vpandn_128(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
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; Force the execution domain with an add.
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%a2 = add <2 x i64> %a, <i64 1, i64 1>
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%y = xor <2 x i64> %a2, <i64 -1, i64 -1>
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%x = and <2 x i64> %a, %y
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ret <2 x i64> %x
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}
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define <4 x i64> @vpor_256(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
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; Force the execution domain with an add.
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%a2 = add <4 x i64> %a, <i64 1, i64 1, i64 1, i64 1>
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%x = or <4 x i64> %a2, %b
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ret <4 x i64> %x
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}
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define <4 x i64> @vpxor_256(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
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; Force the execution domain with an add.
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%a2 = add <4 x i64> %a, <i64 1, i64 1, i64 1, i64 1>
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%x = xor <4 x i64> %a2, %b
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ret <4 x i64> %x
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}
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define <2 x i64> @vpor_128(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
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; Force the execution domain with an add.
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%a2 = add <2 x i64> %a, <i64 1, i64 1>
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%x = or <2 x i64> %a2, %b
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ret <2 x i64> %x
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}
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define <2 x i64> @vpxor_128(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
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; Force the execution domain with an add.
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%a2 = add <2 x i64> %a, <i64 1, i64 1>
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%x = xor <2 x i64> %a2, %b
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ret <2 x i64> %x
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}
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define <4 x i64> @test_vpaddq_256(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
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%x = add <4 x i64> %i, %j
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ret <4 x i64> %x
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}
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define <8 x i32> @test_vpaddd_256(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
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%x = add <8 x i32> %i, %j
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ret <8 x i32> %x
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}
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define <16 x i16> @test_vpaddw_256(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
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%x = add <16 x i16> %i, %j
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ret <16 x i16> %x
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}
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define <32 x i8> @test_vpaddb_256(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
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%x = add <32 x i8> %i, %j
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ret <32 x i8> %x
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}
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define <4 x i64> @test_vpsubq_256(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
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%x = sub <4 x i64> %i, %j
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ret <4 x i64> %x
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}
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define <8 x i32> @test_vpsubd_256(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
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%x = sub <8 x i32> %i, %j
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ret <8 x i32> %x
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}
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define <16 x i16> @test_vpsubw_256(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
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%x = sub <16 x i16> %i, %j
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ret <16 x i16> %x
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}
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define <32 x i8> @test_vpsubb_256(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
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%x = sub <32 x i8> %i, %j
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ret <32 x i8> %x
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}
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define <16 x i16> @test_vpmullw_256(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
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%x = mul <16 x i16> %i, %j
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ret <16 x i16> %x
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}
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define <8 x i32> @test_vpcmpgtd_256(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
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%bincmp = icmp slt <8 x i32> %i, %j
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%x = sext <8 x i1> %bincmp to <8 x i32>
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ret <8 x i32> %x
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}
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define <32 x i8> @test_vpcmpeqb_256(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
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%bincmp = icmp eq <32 x i8> %i, %j
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%x = sext <32 x i1> %bincmp to <32 x i8>
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ret <32 x i8> %x
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}
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define <16 x i16> @test_vpcmpeqw_256(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
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%bincmp = icmp eq <16 x i16> %i, %j
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%x = sext <16 x i1> %bincmp to <16 x i16>
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ret <16 x i16> %x
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}
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define <32 x i8> @test_vpcmpgtb_256(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
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%bincmp = icmp slt <32 x i8> %i, %j
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%x = sext <32 x i1> %bincmp to <32 x i8>
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ret <32 x i8> %x
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}
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define <16 x i16> @test_vpcmpgtw_256(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
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%bincmp = icmp slt <16 x i16> %i, %j
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%x = sext <16 x i1> %bincmp to <16 x i16>
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ret <16 x i16> %x
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}
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define <8 x i32> @test_vpcmpeqd_256(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
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%bincmp = icmp eq <8 x i32> %i, %j
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%x = sext <8 x i1> %bincmp to <8 x i32>
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ret <8 x i32> %x
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}
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define <2 x i64> @test_vpaddq_128(<2 x i64> %i, <2 x i64> %j) nounwind readnone {
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%x = add <2 x i64> %i, %j
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ret <2 x i64> %x
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}
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define <4 x i32> @test_vpaddd_128(<4 x i32> %i, <4 x i32> %j) nounwind readnone {
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%x = add <4 x i32> %i, %j
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ret <4 x i32> %x
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}
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define <8 x i16> @test_vpaddw_128(<8 x i16> %i, <8 x i16> %j) nounwind readnone {
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%x = add <8 x i16> %i, %j
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ret <8 x i16> %x
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}
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define <16 x i8> @test_vpaddb_128(<16 x i8> %i, <16 x i8> %j) nounwind readnone {
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%x = add <16 x i8> %i, %j
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ret <16 x i8> %x
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}
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define <2 x i64> @test_vpsubq_128(<2 x i64> %i, <2 x i64> %j) nounwind readnone {
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%x = sub <2 x i64> %i, %j
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ret <2 x i64> %x
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}
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define <4 x i32> @test_vpsubd_128(<4 x i32> %i, <4 x i32> %j) nounwind readnone {
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%x = sub <4 x i32> %i, %j
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ret <4 x i32> %x
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}
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define <8 x i16> @test_vpsubw_128(<8 x i16> %i, <8 x i16> %j) nounwind readnone {
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%x = sub <8 x i16> %i, %j
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ret <8 x i16> %x
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}
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define <16 x i8> @test_vpsubb_128(<16 x i8> %i, <16 x i8> %j) nounwind readnone {
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%x = sub <16 x i8> %i, %j
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ret <16 x i8> %x
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}
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define <8 x i16> @test_vpmullw_128(<8 x i16> %i, <8 x i16> %j) nounwind readnone {
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%x = mul <8 x i16> %i, %j
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ret <8 x i16> %x
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}
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define <8 x i16> @test_vpcmpgtw_128(<8 x i16> %i, <8 x i16> %j) nounwind readnone {
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%bincmp = icmp slt <8 x i16> %i, %j
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%x = sext <8 x i1> %bincmp to <8 x i16>
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ret <8 x i16> %x
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}
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define <16 x i8> @test_vpcmpgtb_128(<16 x i8> %i, <16 x i8> %j) nounwind readnone {
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%bincmp = icmp slt <16 x i8> %i, %j
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%x = sext <16 x i1> %bincmp to <16 x i8>
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ret <16 x i8> %x
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}
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define <8 x i16> @test_vpcmpeqw_128(<8 x i16> %i, <8 x i16> %j) nounwind readnone {
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%bincmp = icmp eq <8 x i16> %i, %j
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%x = sext <8 x i1> %bincmp to <8 x i16>
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ret <8 x i16> %x
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}
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define <16 x i8> @test_vpcmpeqb_128(<16 x i8> %i, <16 x i8> %j) nounwind readnone {
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%bincmp = icmp eq <16 x i8> %i, %j
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%x = sext <16 x i1> %bincmp to <16 x i8>
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ret <16 x i8> %x
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}
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define <8 x i16> @shuffle_v8i16_vpalignr(<8 x i16> %a, <8 x i16> %b) {
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%shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
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ret <8 x i16> %shuffle
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}
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define <16 x i16> @shuffle_v16i16_vpalignr(<16 x i16> %a, <16 x i16> %b) {
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%shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 23, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 31, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>
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ret <16 x i16> %shuffle
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}
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define <16 x i8> @shuffle_v16i8_vpalignr(<16 x i8> %a, <16 x i8> %b) {
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>
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ret <16 x i8> %shuffle
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}
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define <32 x i8> @shuffle_v32i8_vpalignr(<32 x i8> %a, <32 x i8> %b) {
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%shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 undef, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 63, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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ret <32 x i8> %shuffle
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}
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define <2 x i64> @shuffle_v2i64_vpalignr(<2 x i64> %a, <2 x i64> %b) {
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%shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 2>
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ret <2 x i64> %shuffle
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}
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define <4 x i32> @shuffle_v4i32_vpalignr(<4 x i32> %a, <4 x i32> %b) {
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%shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 0, i32 1, i32 2>
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ret <4 x i32> %shuffle
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}
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define <8 x i32> @shuffle_v8i32_vpalignr(<8 x i32> %a, <8 x i32> %b) {
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%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 11, i32 0, i32 1, i32 2, i32 15, i32 4, i32 5, i32 6>
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ret <8 x i32> %shuffle
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}
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define <4 x double> @shuffle_v4f64_5163(<4 x double> %a, <4 x double> %b) {
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 5, i32 1, i32 6, i32 3>
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ret <4 x double> %shuffle
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}
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define <2 x double> @shuffle_v2f64_bitcast_1z(<2 x double> %a) {
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%shuffle64 = shufflevector <2 x double> %a, <2 x double> zeroinitializer, <2 x i32> <i32 2, i32 1>
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%bitcast32 = bitcast <2 x double> %shuffle64 to <4 x float>
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%shuffle32 = shufflevector <4 x float> %bitcast32, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
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%bitcast64 = bitcast <4 x float> %shuffle32 to <2 x double>
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ret <2 x double> %bitcast64
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}
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define <16 x i16> @shuffle_v16i16_zz_zz_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_24(<16 x i16> %a) {
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%shuffle = shufflevector <16 x i16> zeroinitializer, <16 x i16> %a, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 16, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 24>
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ret <16 x i16> %shuffle
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}
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define i64 @extract_v2i64(<2 x i64> %x, i64* %dst) {
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%r1 = extractelement <2 x i64> %x, i32 0
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%r2 = extractelement <2 x i64> %x, i32 1
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store i64 %r2, i64* %dst, align 1
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ret i64 %r1
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}
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define i32 @extract_v4i32(<4 x i32> %x, i32* %dst) {
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%r1 = extractelement <4 x i32> %x, i32 1
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%r2 = extractelement <4 x i32> %x, i32 3
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store i32 %r2, i32* %dst, align 1
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ret i32 %r1
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}
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define i16 @extract_v8i16(<8 x i16> %x, i16* %dst) {
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%r1 = extractelement <8 x i16> %x, i32 1
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%r2 = extractelement <8 x i16> %x, i32 3
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store i16 %r2, i16* %dst, align 1
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ret i16 %r1
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}
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define i8 @extract_v16i8(<16 x i8> %x, i8* %dst) {
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%r1 = extractelement <16 x i8> %x, i32 1
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%r2 = extractelement <16 x i8> %x, i32 3
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store i8 %r2, i8* %dst, align 1
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ret i8 %r1
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}
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define <2 x i64> @insert_v2i64(<2 x i64> %x, i64 %y , i64* %ptr) {
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%val = load i64, i64* %ptr
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%r1 = insertelement <2 x i64> %x, i64 %val, i32 1
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%r2 = insertelement <2 x i64> %r1, i64 %y, i32 3
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ret <2 x i64> %r2
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}
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define <4 x i32> @insert_v4i32(<4 x i32> %x, i32 %y, i32* %ptr) {
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%val = load i32, i32* %ptr
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%r1 = insertelement <4 x i32> %x, i32 %val, i32 1
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%r2 = insertelement <4 x i32> %r1, i32 %y, i32 3
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ret <4 x i32> %r2
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}
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define <8 x i16> @insert_v8i16(<8 x i16> %x, i16 %y, i16* %ptr) {
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%val = load i16, i16* %ptr
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%r1 = insertelement <8 x i16> %x, i16 %val, i32 1
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%r2 = insertelement <8 x i16> %r1, i16 %y, i32 5
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ret <8 x i16> %r2
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}
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define <16 x i8> @insert_v16i8(<16 x i8> %x, i8 %y, i8* %ptr) {
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%val = load i8, i8* %ptr
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%r1 = insertelement <16 x i8> %x, i8 %val, i32 3
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%r2 = insertelement <16 x i8> %r1, i8 %y, i32 10
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ret <16 x i8> %r2
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}
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