forked from OSchip/llvm-project
259 lines
7.5 KiB
LLVM
259 lines
7.5 KiB
LLVM
; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-T1
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; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs -mcpu=cortex-m0 | FileCheck %s --check-prefix=CHECK-M0
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define void @func(i32 %argc, i8** %argv) nounwind {
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entry:
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%argc.addr = alloca i32 ; <i32*> [#uses=1]
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%argv.addr = alloca i8** ; <i8***> [#uses=1]
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%val1 = alloca i32 ; <i32*> [#uses=2]
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%val2 = alloca i32 ; <i32*> [#uses=15]
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%andt = alloca i32 ; <i32*> [#uses=2]
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%ort = alloca i32 ; <i32*> [#uses=2]
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%xort = alloca i32 ; <i32*> [#uses=2]
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%old = alloca i32 ; <i32*> [#uses=18]
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%temp = alloca i32 ; <i32*> [#uses=2]
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store i32 %argc, i32* %argc.addr
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store i8** %argv, i8*** %argv.addr
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store i32 0, i32* %val1
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store i32 31, i32* %val2
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store i32 3855, i32* %andt
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store i32 3855, i32* %ort
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store i32 3855, i32* %xort
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store i32 4, i32* %temp
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%tmp = load i32* %temp
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; CHECK: ldrex
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; CHECK: add
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; CHECK: strex
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; CHECK-T1: blx ___sync_fetch_and_add_4
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; CHECK-M0: bl ___sync_fetch_and_add_4
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%0 = atomicrmw add i32* %val1, i32 %tmp monotonic
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store i32 %0, i32* %old
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; CHECK: ldrex
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; CHECK: sub
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; CHECK: strex
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; CHECK-T1: blx ___sync_fetch_and_sub_4
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; CHECK-M0: bl ___sync_fetch_and_sub_4
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%1 = atomicrmw sub i32* %val2, i32 30 monotonic
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store i32 %1, i32* %old
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; CHECK: ldrex
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; CHECK: add
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; CHECK: strex
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; CHECK-T1: blx ___sync_fetch_and_add_4
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; CHECK-M0: bl ___sync_fetch_and_add_4
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%2 = atomicrmw add i32* %val2, i32 1 monotonic
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store i32 %2, i32* %old
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; CHECK: ldrex
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; CHECK: sub
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; CHECK: strex
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; CHECK-T1: blx ___sync_fetch_and_sub_4
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; CHECK-M0: bl ___sync_fetch_and_sub_4
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%3 = atomicrmw sub i32* %val2, i32 1 monotonic
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store i32 %3, i32* %old
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; CHECK: ldrex
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; CHECK: and
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; CHECK: strex
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; CHECK-T1: blx ___sync_fetch_and_and_4
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; CHECK-M0: bl ___sync_fetch_and_and_4
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%4 = atomicrmw and i32* %andt, i32 4080 monotonic
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store i32 %4, i32* %old
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; CHECK: ldrex
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; CHECK: or
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; CHECK: strex
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; CHECK-T1: blx ___sync_fetch_and_or_4
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; CHECK-M0: bl ___sync_fetch_and_or_4
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%5 = atomicrmw or i32* %ort, i32 4080 monotonic
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store i32 %5, i32* %old
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; CHECK: ldrex
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; CHECK: eor
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; CHECK: strex
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; CHECK-T1: blx ___sync_fetch_and_xor_4
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; CHECK-M0: bl ___sync_fetch_and_xor_4
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%6 = atomicrmw xor i32* %xort, i32 4080 monotonic
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store i32 %6, i32* %old
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; CHECK: ldrex
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; CHECK: cmp
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; CHECK: strex
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; CHECK-T1: blx ___sync_fetch_and_min_4
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; CHECK-M0: bl ___sync_fetch_and_min_4
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%7 = atomicrmw min i32* %val2, i32 16 monotonic
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store i32 %7, i32* %old
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%neg = sub i32 0, 1
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; CHECK: ldrex
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; CHECK: cmp
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; CHECK: strex
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; CHECK-T1: blx ___sync_fetch_and_min_4
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; CHECK-M0: bl ___sync_fetch_and_min_4
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%8 = atomicrmw min i32* %val2, i32 %neg monotonic
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store i32 %8, i32* %old
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; CHECK: ldrex
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; CHECK: cmp
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; CHECK: strex
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; CHECK-T1: blx ___sync_fetch_and_max_4
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; CHECK-M0: bl ___sync_fetch_and_max_4
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%9 = atomicrmw max i32* %val2, i32 1 monotonic
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store i32 %9, i32* %old
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; CHECK: ldrex
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; CHECK: cmp
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; CHECK: strex
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; CHECK-T1: blx ___sync_fetch_and_max_4
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; CHECK-M0: bl ___sync_fetch_and_max_4
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%10 = atomicrmw max i32* %val2, i32 0 monotonic
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store i32 %10, i32* %old
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; CHECK: ldrex
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; CHECK: cmp
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; CHECK: strex
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; CHECK-T1: blx ___sync_fetch_and_umin_4
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; CHECK-M0: bl ___sync_fetch_and_umin_4
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%11 = atomicrmw umin i32* %val2, i32 16 monotonic
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store i32 %11, i32* %old
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%uneg = sub i32 0, 1
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; CHECK: ldrex
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; CHECK: cmp
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; CHECK: strex
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; CHECK-T1: blx ___sync_fetch_and_umin_4
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; CHECK-M0: bl ___sync_fetch_and_umin_4
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%12 = atomicrmw umin i32* %val2, i32 %uneg monotonic
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store i32 %12, i32* %old
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; CHECK: ldrex
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; CHECK: cmp
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; CHECK: strex
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; CHECK-T1: blx ___sync_fetch_and_umax_4
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; CHECK-M0: bl ___sync_fetch_and_umax_4
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%13 = atomicrmw umax i32* %val2, i32 1 monotonic
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store i32 %13, i32* %old
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; CHECK: ldrex
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; CHECK: cmp
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; CHECK: strex
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; CHECK-T1: blx ___sync_fetch_and_umax_4
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; CHECK-M0: bl ___sync_fetch_and_umax_4
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%14 = atomicrmw umax i32* %val2, i32 0 monotonic
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store i32 %14, i32* %old
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ret void
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}
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define void @func2() nounwind {
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entry:
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%val = alloca i16
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%old = alloca i16
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store i16 31, i16* %val
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; CHECK: ldrex
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; CHECK: cmp
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; CHECK: strex
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; CHECK-T1: blx ___sync_fetch_and_umin_2
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; CHECK-M0: bl ___sync_fetch_and_umin_2
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%0 = atomicrmw umin i16* %val, i16 16 monotonic
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store i16 %0, i16* %old
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%uneg = sub i16 0, 1
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; CHECK: ldrex
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; CHECK: cmp
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; CHECK: strex
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; CHECK-T1: blx ___sync_fetch_and_umin_2
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; CHECK-M0: bl ___sync_fetch_and_umin_2
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%1 = atomicrmw umin i16* %val, i16 %uneg monotonic
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store i16 %1, i16* %old
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; CHECK: ldrex
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; CHECK: cmp
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; CHECK: strex
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; CHECK-T1: blx ___sync_fetch_and_umax_2
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; CHECK-M0: bl ___sync_fetch_and_umax_2
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%2 = atomicrmw umax i16* %val, i16 1 monotonic
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store i16 %2, i16* %old
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; CHECK: ldrex
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; CHECK: cmp
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; CHECK: strex
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; CHECK-T1: blx ___sync_fetch_and_umax_2
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; CHECK-M0: bl ___sync_fetch_and_umax_2
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%3 = atomicrmw umax i16* %val, i16 0 monotonic
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store i16 %3, i16* %old
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ret void
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}
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define void @func3() nounwind {
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entry:
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%val = alloca i8
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%old = alloca i8
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store i8 31, i8* %val
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; CHECK: ldrex
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; CHECK: cmp
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; CHECK: strex
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; CHECK-T1: blx ___sync_fetch_and_umin_1
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; CHECK-M0: bl ___sync_fetch_and_umin_1
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%0 = atomicrmw umin i8* %val, i8 16 monotonic
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store i8 %0, i8* %old
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; CHECK: ldrex
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; CHECK: cmp
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; CHECK: strex
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; CHECK-T1: blx ___sync_fetch_and_umin_1
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; CHECK-M0: bl ___sync_fetch_and_umin_1
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%uneg = sub i8 0, 1
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%1 = atomicrmw umin i8* %val, i8 %uneg monotonic
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store i8 %1, i8* %old
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; CHECK: ldrex
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; CHECK: cmp
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; CHECK: strex
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; CHECK-T1: blx ___sync_fetch_and_umax_1
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; CHECK-M0: bl ___sync_fetch_and_umax_1
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%2 = atomicrmw umax i8* %val, i8 1 monotonic
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store i8 %2, i8* %old
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; CHECK: ldrex
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; CHECK: cmp
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; CHECK: strex
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; CHECK-T1: blx ___sync_fetch_and_umax_1
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; CHECK-M0: bl ___sync_fetch_and_umax_1
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%3 = atomicrmw umax i8* %val, i8 0 monotonic
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store i8 %3, i8* %old
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ret void
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}
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; CHECK: func4
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; This function should not need to use callee-saved registers.
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; rdar://problem/12203728
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; CHECK-NOT: r4
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define i32 @func4(i32* %p) nounwind optsize ssp {
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entry:
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%0 = atomicrmw add i32* %p, i32 1 monotonic
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ret i32 %0
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}
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define i32 @test_cmpxchg_fail_order(i32 *%addr, i32 %desired, i32 %new) {
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; CHECK-LABEL: test_cmpxchg_fail_order:
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%pair = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic
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%oldval = extractvalue { i32, i1 } %pair, 0
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; CHECK: dmb ish
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; CHECK: [[LOOP_BB:\.?LBB[0-9]+_1]]:
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; CHECK: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]]
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; CHECK: cmp [[OLDVAL]], r1
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; CHECK: bxne lr
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; CHECK: strex [[SUCCESS:r[0-9]+]], r2, [r[[ADDR]]]
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; CHECK: cmp [[SUCCESS]], #0
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; CHECK: bne [[LOOP_BB]]
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; CHECK: dmb ish
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; CHECK: bx lr
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ret i32 %oldval
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}
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define i32 @test_cmpxchg_fail_order1(i32 *%addr, i32 %desired, i32 %new) {
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; CHECK-LABEL: test_cmpxchg_fail_order1:
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%pair = cmpxchg i32* %addr, i32 %desired, i32 %new acquire acquire
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%oldval = extractvalue { i32, i1 } %pair, 0
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; CHECK-NOT: dmb ish
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; CHECK: [[LOOP_BB:\.?LBB[0-9]+_1]]:
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; CHECK: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]]
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; CHECK: cmp [[OLDVAL]], r1
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; CHECK: bne [[END_BB:\.?LBB[0-9]+_[0-9]+]]
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; CHECK: strex [[SUCCESS:r[0-9]+]], r2, [r[[ADDR]]]
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; CHECK: cmp [[SUCCESS]], #0
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; CHECK: bne [[LOOP_BB]]
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; CHECK: [[END_BB]]:
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; CHECK: dmb ish
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; CHECK: bx lr
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ret i32 %oldval
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}
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