forked from OSchip/llvm-project
175 lines
8.6 KiB
TableGen
175 lines
8.6 KiB
TableGen
//===---- X86InstrAMX.td - AMX Instruction Set Extension --*- tablegen -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the instructions that make up the Intel AMX instruction
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// set.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// AMX instructions
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let Predicates = [HasAMXTILE, In64BitMode] in {
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let SchedRW = [WriteSystem] in {
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let hasSideEffects = 1,
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Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
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def LDTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src),
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"ldtilecfg\t$src",
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[(int_x86_ldtilecfg addr:$src)]>, VEX, T8PS;
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let hasSideEffects = 1 in
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def STTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src),
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"sttilecfg\t$src",
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[(int_x86_sttilecfg addr:$src)]>, VEX, T8PD;
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let mayLoad = 1 in
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def TILELOADD : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
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(ins sibmem:$src),
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"tileloadd\t{$src, $dst|$dst, $src}", []>,
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VEX, T8XD;
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let mayLoad = 1 in
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def TILELOADDT1 : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
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(ins sibmem:$src),
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"tileloaddt1\t{$src, $dst|$dst, $src}", []>,
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VEX, T8PD;
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let Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
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def TILERELEASE : I<0x49, MRM_C0, (outs), (ins),
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"tilerelease", [(int_x86_tilerelease)]>, VEX, T8PS;
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let mayStore = 1 in
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def TILESTORED : I<0x4b, MRMDestMemFSIB, (outs),
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(ins sibmem:$dst, TILE:$src),
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"tilestored\t{$src, $dst|$dst, $src}", []>,
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VEX, T8XS;
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def TILEZERO : I<0x49, MRMr0, (outs TILE:$dst), (ins),
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"tilezero\t$dst", []>,
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VEX, T8XD;
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// Pseduo instruction for RA.
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def PTILELOADDV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
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GR16:$src2,
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opaquemem:$src3), []>;
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def PTILESTOREDV : PseudoI<(outs), (ins GR16:$src1,
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GR16:$src2, opaquemem:$src3,
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TILE:$src4), []>;
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let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1 in
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def PTILEZEROV : PseudoI<(outs TILE:$dst), (ins GR16:$src1, GR16:$src2),
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[(set TILE:$dst, (int_x86_tilezero_internal
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GR16:$src1, GR16:$src2))]>;
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let usesCustomInserter = 1 in {
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// Pseudo instructions, using immediates instead of tile registers.
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// To be translated to the actual instructions in X86ISelLowering.cpp
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def PTILELOADD : PseudoI<(outs), (ins u8imm:$src1, sibmem:$src2), []>;
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def PTILELOADDT1 : PseudoI<(outs), (ins u8imm:$src1,
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sibmem:$src2), []>;
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def PTILESTORED : PseudoI<(outs), (ins i8mem:$dst, u8imm:$src), []>;
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def PTILEZERO : PseudoI<(outs), (ins u8imm:$src),
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[(int_x86_tilezero timm:$src)]>;
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}
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} // SchedRW
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} // HasAMXTILE
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let Predicates = [HasAMXINT8, In64BitMode] in {
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let SchedRW = [WriteSystem] in {
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let Constraints = "$src1 = $dst" in {
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def TDPBSSD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
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(ins TILE:$src1, TILE:$src2, TILE:$src3),
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"tdpbssd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
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VEX_4V, T8XD;
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def TDPBSUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
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(ins TILE:$src1, TILE:$src2, TILE:$src3),
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"tdpbsud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
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VEX_4V, T8XS;
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def TDPBUSD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
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(ins TILE:$src1, TILE:$src2, TILE:$src3),
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"tdpbusd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
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VEX_4V, T8PD;
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def TDPBUUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
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(ins TILE:$src1, TILE:$src2, TILE:$src3),
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"tdpbuud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
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VEX_4V, T8PS;
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}
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// Pseduo instruction for RA.
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let Constraints = "$src4 = $dst" in {
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def PTDPBSSDV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
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GR16:$src2, GR16:$src3, TILE:$src4,
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TILE:$src5, TILE:$src6),
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[(set TILE: $dst,
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(int_x86_tdpbssd_internal GR16:$src1, GR16:$src2,
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GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
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def PTDPBSUDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
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GR16:$src2, GR16:$src3, TILE:$src4,
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TILE:$src5, TILE:$src6),
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[(set TILE: $dst,
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(int_x86_tdpbsud_internal GR16:$src1, GR16:$src2,
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GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
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def PTDPBUSDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
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GR16:$src2, GR16:$src3, TILE:$src4,
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TILE:$src5, TILE:$src6),
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[(set TILE: $dst,
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(int_x86_tdpbusd_internal GR16:$src1, GR16:$src2,
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GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
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def PTDPBUUDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
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GR16:$src2, GR16:$src3, TILE:$src4,
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TILE:$src5, TILE:$src6),
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[(set TILE: $dst,
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(int_x86_tdpbuud_internal GR16:$src1, GR16:$src2,
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GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
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}
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let usesCustomInserter = 1 in {
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// Pseudo instructions, using immediates instead of tile registers.
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// To be translated to the actual instructions in X86ISelLowering.cpp
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def PTDPBSSD : PseudoI<(outs), (ins u8imm:$src1,
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u8imm:$src2, u8imm:$src3),
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[(int_x86_tdpbssd timm:$src1,
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timm:$src2, timm:$src3)]>;
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def PTDPBSUD : PseudoI<(outs), (ins u8imm:$src1,
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u8imm:$src2, u8imm:$src3),
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[(int_x86_tdpbsud timm:$src1,
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timm:$src2, timm:$src3)]>;
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def PTDPBUSD : PseudoI<(outs), (ins u8imm:$src1,
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u8imm:$src2, u8imm:$src3),
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[(int_x86_tdpbusd timm:$src1,
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timm:$src2, timm:$src3)]>;
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def PTDPBUUD : PseudoI<(outs), (ins u8imm:$src1,
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u8imm:$src2, u8imm:$src3),
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[(int_x86_tdpbuud timm:$src1,
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timm:$src2, timm:$src3)]>;
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}
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}
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} // HasAMXTILE
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let Predicates = [HasAMXBF16, In64BitMode] in {
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let SchedRW = [WriteSystem] in {
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let Constraints = "$src1 = $dst" in
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def TDPBF16PS : I<0x5c, MRMSrcReg4VOp3, (outs TILE:$dst),
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(ins TILE:$src1, TILE:$src2, TILE:$src3),
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"tdpbf16ps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[]>, VEX_4V, T8XS;
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// Pseduo instruction for RA.
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let Constraints = "$src4 = $dst" in
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def PTDPBF16PSV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
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GR16:$src2, GR16:$src3, TILE:$src4,
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TILE:$src5, TILE:$src6),
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[(set TILE: $dst,
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(int_x86_tdpbf16ps_internal GR16:$src1,
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GR16:$src2, GR16:$src3, TILE:$src4,
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TILE:$src5, TILE:$src6))]>;
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let usesCustomInserter = 1 in {
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// Pseudo instructions, using immediates instead of tile registers.
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// To be translated to the actual instructions in X86ISelLowering.cpp
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def PTDPBF16PS : PseudoI<(outs), (ins u8imm:$src1,
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u8imm:$src2, u8imm:$src3),
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[(int_x86_tdpbf16ps timm:$src1,
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timm:$src2, timm:$src3)]>;
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}
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}
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} // HasAMXTILE, HasAMXBF16
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