llvm-project/llvm/lib/Target/RISCV
Craig Topper c82f442954 [RISCV] Support fixed vector copysign.
Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D98394
2021-03-11 09:57:24 -08:00
..
AsmParser [RISCV] Change parseVTypeI function 2021-02-12 19:38:34 +08:00
Disassembler [RISCV] Fix shared libs build 2021-02-09 06:14:25 -06:00
MCTargetDesc [MC][RISCV] Support .reloc *, BFD_RELOC_{NONE,32,64}, * 2021-03-05 21:45:11 -08:00
TargetInfo llvmbuildectomy - replace llvm-build by plain cmake 2020-11-13 10:35:24 +01:00
CMakeLists.txt [RISCV] Merge Utils library into MCTargetDesc 2021-01-14 11:47:30 -08:00
RISCV.h [RISCV] Merge Utils library into MCTargetDesc 2021-01-14 11:47:30 -08:00
RISCV.td [RISCV] Fix name of Zba extension (NFC) 2021-01-24 21:02:34 +00:00
RISCVAsmPrinter.cpp [RISCV] Add -mtune support 2020-10-16 13:55:08 +08:00
RISCVCallLowering.cpp [GlobalISel] Base implementation for sret demotion. 2021-01-06 10:30:50 +05:30
RISCVCallLowering.h [GlobalISel] Base implementation for sret demotion. 2021-01-06 10:30:50 +05:30
RISCVCallingConv.td
RISCVCleanupVSETVLI.cpp [RISCV] Teach CleanupVSETVLI to remove 'vsetvli zero, zero, vtype' when the vtype matches the previous vsetvli or vsetivli 2021-02-25 07:51:19 -08:00
RISCVExpandAtomicPseudoInsts.cpp [RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos 2020-07-15 10:50:55 +01:00
RISCVExpandPseudoInsts.cpp [RISCV] Add new vector instructions in v0.10. 2021-02-03 13:28:58 +08:00
RISCVFrameLowering.cpp [RISCV] Simplify BP initialisation 2021-02-17 20:33:20 +08:00
RISCVFrameLowering.h [RISCV] Frame handling for RISC-V V extension. 2021-02-17 14:05:19 +08:00
RISCVISelDAGToDAG.cpp [RISCV] Fix crash when inserting large fixed-length subvectors 2021-03-04 09:27:16 +00:00
RISCVISelDAGToDAG.h [RISCV] Use a ComplexPattern for zexti32 to match sexti32. 2021-02-24 16:06:29 -08:00
RISCVISelLowering.cpp [RISCV] Support fixed vector copysign. 2021-03-11 09:57:24 -08:00
RISCVISelLowering.h [RISCV] Support fixed vector copysign. 2021-03-11 09:57:24 -08:00
RISCVInstrFormats.td [RISCV] Make scalable vector FMA commutable for register allocation. 2021-02-08 10:05:33 -08:00
RISCVInstrFormatsC.td
RISCVInstrFormatsV.td [RISCV] Add new vector instructions in v0.10. 2021-02-03 13:28:58 +08:00
RISCVInstrInfo.cpp [RISCV] Make the hasStdExtM() check in RISCVInstrInfo::getVLENFactoredAmount emit a diagnostic rather than an assert. 2021-03-09 08:50:02 -08:00
RISCVInstrInfo.h [RISCV] Make the hasStdExtM() check in RISCVInstrInfo::getVLENFactoredAmount emit a diagnostic rather than an assert. 2021-03-09 08:50:02 -08:00
RISCVInstrInfo.td [RISCV] Add explicit i64 types to RV64 isel patterns to stop tablegen from generating unneeded i32 patterns for RV32 HwMode. 2021-03-08 09:06:56 -08:00
RISCVInstrInfoA.td [RISCV] Add explicit i64 types to RV64 isel patterns to stop tablegen from generating unneeded i32 patterns for RV32 HwMode. 2021-03-08 09:06:56 -08:00
RISCVInstrInfoB.td [RISCV] Move SHFLI matching to DAG combine. Add 32-bit support for RV64 2021-02-19 10:07:12 -08:00
RISCVInstrInfoC.td [RISCV] More whitespace and comment typo fixes in RISCVInstrInfoC.td 2021-02-11 02:32:36 +00:00
RISCVInstrInfoD.td [RISCV] Use a ComplexPattern for zexti32 to match sexti32. 2021-02-24 16:06:29 -08:00
RISCVInstrInfoF.td [RISCV] Use a ComplexPattern for zexti32 to match sexti32. 2021-02-24 16:06:29 -08:00
RISCVInstrInfoM.td [RISCV] Add explicit i64 types to RV64 isel patterns to stop tablegen from generating unneeded i32 patterns for RV32 HwMode. 2021-03-08 09:06:56 -08:00
RISCVInstrInfoV.td [RISCV][MC] Fix nf encoding for vector ld/st whole register 2021-03-08 19:30:24 -08:00
RISCVInstrInfoVPseudos.td [RISCV] Starting fixing issues that prevent us from testing vXi64 intrinsics on RV32. 2021-03-10 09:45:38 -08:00
RISCVInstrInfoVSDPatterns.td [RISCV] Add support for fixed vector reductions. 2021-03-09 09:39:59 -08:00
RISCVInstrInfoVVLPatterns.td [RISCV] Support fixed vector copysign. 2021-03-11 09:57:24 -08:00
RISCVInstrInfoZfh.td [RISCV] Use a ComplexPattern for zexti32 to match sexti32. 2021-02-24 16:06:29 -08:00
RISCVInstructionSelector.cpp RISCV: Avoid GlobalISel build break in a future patch 2020-07-13 14:01:57 -04:00
RISCVLegalizerInfo.cpp
RISCVLegalizerInfo.h
RISCVMCInstLower.cpp [RISCV] Define different pseudo instructions for different FPR. 2021-01-26 15:48:35 +08:00
RISCVMachineFunctionInfo.h [RISCV] Frame handling for RISC-V V extension. 2021-02-17 14:05:19 +08:00
RISCVMergeBaseOffset.cpp [RISCV] Support Zfh half-precision floating-point extension. 2020-12-03 09:16:33 +08:00
RISCVRegisterBankInfo.cpp
RISCVRegisterBankInfo.h
RISCVRegisterBanks.td
RISCVRegisterInfo.cpp [RISCV] Improve register allocation around vector masks 2021-02-20 14:47:51 +00:00
RISCVRegisterInfo.h [RISCV] Improve register allocation around vector masks 2021-02-20 14:47:51 +00:00
RISCVRegisterInfo.td [RISCV] Use XLenRI alias for RegInfoByHwMode instances 2021-02-18 19:38:36 +00:00
RISCVSchedRocket.td [RISCV] Fix formatting (NFC) 2020-09-25 18:15:04 -05:00
RISCVSchedSiFive7.td [RISCV] Use the commercial name for scheduling model (NFC) 2020-10-23 16:33:27 -05:00
RISCVSchedule.td [RISCV] Fix formatting (NFC) 2020-09-25 18:15:04 -05:00
RISCVSubtarget.cpp [RISCV] Add support loads, stores, and splats of vXi1 fixed vectors. 2021-02-11 09:13:16 -08:00
RISCVSubtarget.h [RISCV] Make the min and max vector width command line options more consistent and check their relationship to each other. 2021-02-09 10:47:23 -08:00
RISCVSystemOperands.td [RISCV] Enable the use of the old mucounteren name 2020-08-17 13:11:49 +01:00
RISCVTargetMachine.cpp [AArch64][GlobalISel] Enable use of the optsize predicate in the selector. 2021-03-02 12:55:51 -08:00
RISCVTargetMachine.h [RISCV] Address clang-tidy warnings in RISCVTargetMachine. NFC. 2020-12-18 21:50:55 +00:00
RISCVTargetObjectFile.cpp ELF: Create unique SHF_GNU_RETAIN sections for llvm.used global objects 2021-02-26 16:38:44 -08:00
RISCVTargetObjectFile.h
RISCVTargetTransformInfo.cpp [RISCV] Make the min and max vector width command line options more consistent and check their relationship to each other. 2021-02-09 10:47:23 -08:00
RISCVTargetTransformInfo.h [RISCV] Enable fixed-length vectorization of LoopVectorizer for RISC-V Vector 2021-03-05 10:54:51 +08:00