forked from OSchip/llvm-project
36 lines
1.1 KiB
LLVM
36 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-- | FileCheck %s
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; These tests differ from the ones in zext-inreg-0.ll in that
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; on x86-64 they do require and instructions.
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; These should use movzbl instead of 'and 255'.
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; This related to not having ZERO_EXTEND_REG node.
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define i64 @l(i64 %d) nounwind {
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; CHECK-LABEL: l:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: addl $1, %eax
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; CHECK-NEXT: adcl $0, %ecx
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; CHECK-NEXT: movzbl %cl, %edx
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; CHECK-NEXT: retl
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%e = add i64 %d, 1
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%retval = and i64 %e, 1099511627775
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ret i64 %retval
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}
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define i64 @m(i64 %d) nounwind {
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; CHECK-LABEL: m:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: addl $1, %eax
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; CHECK-NEXT: adcl $0, %ecx
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; CHECK-NEXT: movzwl %cx, %edx
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; CHECK-NEXT: retl
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%e = add i64 %d, 1
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%retval = and i64 %e, 281474976710655
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ret i64 %retval
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}
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