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llvm-project/llvm/test/CodeGen
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Craig Topper c06e53119b [X86] Use 128-bit vector instructions for f32/f64->i64 conversions on 32-bit targets with avx512dq and avx512vl instructions. 
On 32-bit targets we can't use the scalar instruction so we
insert the scalar into a vector and use packed conversions.
Previously we used either v4f32->v4i64 or v4f64->v4i64 to avoid
some complexity creating target specific ISD opcodes for
v4f32->v2i64. But this causes extra vzeroupper instructions and
possibly frequency throttling on Intel CPUs.

This patch changes this to create a 128-bit vector and uses a
target specific ISD opcode if needed.
 		2019-12-24 11:20:10 -08:00
..
AArch64 [DAGCombine] visitEXTRACT_SUBVECTOR - 'little to big' extract_subvector(bitcast()) support 2019-12-23 10:11:45 -05:00
AMDGPU AMDGPU/GlobalISel: Legalize some 16-bit round instructions 2019-12-24 09:53:01 -05:00
ARC
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ARM [DAGCombine] visitEXTRACT_SUBVECTOR - 'little to big' extract_subvector(bitcast()) support 2019-12-23 10:11:45 -05:00
AVR [AVR] Fix codegen for rotate instructions 2019-12-23 11:41:28 +08:00
BPF [BPF] put not-section-attribute externs into BTF ".extern" data section 2019-12-10 11:45:17 -08:00
Generic [CodeGen] [ExpandReduction] Fix the bug for ExpandReduction() when vector size isn't power of 2 2019-11-02 23:59:12 -04:00
Hexagon [ModuloSchedule] Fix a bug in experimental expander 2019-11-23 16:01:47 -08:00
Inputs
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Lanai
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MIR [llvm][MIRVRegNamerUtils] Adding hashing on CImm / FPImm MachineOperands. 2019-12-16 18:25:04 -05:00
MSP430 [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine (4) 2019-11-13 09:23:08 +01:00
Mips Mips: Make test resistant to future changes 2019-12-21 04:56:20 -05:00
NVPTX [NVPTX] Added llvm.nvvm.mma.m8n8k4.* intrinsics 2019-10-28 13:55:30 -07:00
PowerPC [PowerPC] NFC - fix the testcase bug of folding rlwinm 2019-12-23 10:28:22 -05:00
RISCV [RISCV][NFC] Fix use of missing attribute groups in tests 2019-12-23 15:39:04 +00:00
SPARC Temporarily run machine-verifier once in test/CodeGen/SPARC/fp128.ll, so that 2019-12-03 11:21:52 +01:00
SystemZ [FPEnv][X86] More strict int <-> FP conversion fixes 2019-12-23 21:11:45 +01:00
Thumb Revert "ARM-Darwin: keep the frame register reserved even if not updated." 2019-12-06 10:59:26 -08:00
Thumb2 [ARM][MVE] Fixes for tail predication. 2019-12-20 09:34:18 +00:00
WebAssembly [WebAssembly] Add avgr_u intrinsics and require nuw in patterns 2019-12-18 15:31:38 -08:00
WinCFGuard [WinCFG] Handle constant casts carefully in .gfids emission 2019-11-01 13:32:03 -07:00
WinEH
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X86 [X86] Use 128-bit vector instructions for f32/f64->i64 conversions on 32-bit targets with avx512dq and avx512vl instructions. 2019-12-24 11:20:10 -08:00
XCore
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