forked from OSchip/llvm-project
282 lines
9.1 KiB
C++
282 lines
9.1 KiB
C++
//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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/// \file
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class AMDGPUTargetMachine;
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class FunctionPass;
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class GCNTargetMachine;
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class ModulePass;
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class Pass;
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class Target;
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class TargetMachine;
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class TargetOptions;
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class PassRegistry;
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class Module;
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// R600 Passes
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FunctionPass *createR600VectorRegMerger();
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FunctionPass *createR600ExpandSpecialInstrsPass();
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FunctionPass *createR600EmitClauseMarkers();
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FunctionPass *createR600ClauseMergePass();
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FunctionPass *createR600Packetizer();
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FunctionPass *createR600ControlFlowFinalizer();
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FunctionPass *createAMDGPUCFGStructurizerPass();
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FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel);
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// SI Passes
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FunctionPass *createSIAnnotateControlFlowPass();
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FunctionPass *createSIFoldOperandsPass();
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FunctionPass *createSIPeepholeSDWAPass();
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FunctionPass *createSILowerI1CopiesPass();
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FunctionPass *createSIShrinkInstructionsPass();
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FunctionPass *createSILoadStoreOptimizerPass();
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FunctionPass *createSIWholeQuadModePass();
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FunctionPass *createSIFixControlFlowLiveIntervalsPass();
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FunctionPass *createSIOptimizeExecMaskingPreRAPass();
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FunctionPass *createSIFixSGPRCopiesPass();
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FunctionPass *createSIMemoryLegalizerPass();
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FunctionPass *createSIDebuggerInsertNopsPass();
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FunctionPass *createSIInsertWaitcntsPass();
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FunctionPass *createSIFixWWMLivenessPass();
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FunctionPass *createSIFormMemoryClausesPass();
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FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetOptions &);
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FunctionPass *createAMDGPUUseNativeCallsPass();
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FunctionPass *createAMDGPUCodeGenPreparePass();
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FunctionPass *createAMDGPUMachineCFGStructurizerPass();
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FunctionPass *createAMDGPURewriteOutArgumentsPass();
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void initializeAMDGPUDAGToDAGISelPass(PassRegistry&);
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void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&);
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extern char &AMDGPUMachineCFGStructurizerID;
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void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
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Pass *createAMDGPUAnnotateKernelFeaturesPass();
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void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
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extern char &AMDGPUAnnotateKernelFeaturesID;
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ModulePass *createAMDGPULowerIntrinsicsPass();
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void initializeAMDGPULowerIntrinsicsPass(PassRegistry &);
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extern char &AMDGPULowerIntrinsicsID;
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FunctionPass *createAMDGPULowerKernelArgumentsPass();
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void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &);
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extern char &AMDGPULowerKernelArgumentsID;
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ModulePass *createAMDGPULowerKernelAttributesPass();
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void initializeAMDGPULowerKernelAttributesPass(PassRegistry &);
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extern char &AMDGPULowerKernelAttributesID;
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void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
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extern char &AMDGPURewriteOutArgumentsID;
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void initializeR600ClauseMergePassPass(PassRegistry &);
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extern char &R600ClauseMergePassID;
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void initializeR600ControlFlowFinalizerPass(PassRegistry &);
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extern char &R600ControlFlowFinalizerID;
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void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &);
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extern char &R600ExpandSpecialInstrsPassID;
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void initializeR600VectorRegMergerPass(PassRegistry &);
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extern char &R600VectorRegMergerID;
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void initializeR600PacketizerPass(PassRegistry &);
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extern char &R600PacketizerID;
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void initializeSIFoldOperandsPass(PassRegistry &);
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extern char &SIFoldOperandsID;
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void initializeSIPeepholeSDWAPass(PassRegistry &);
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extern char &SIPeepholeSDWAID;
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void initializeSIShrinkInstructionsPass(PassRegistry&);
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extern char &SIShrinkInstructionsID;
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void initializeSIFixSGPRCopiesPass(PassRegistry &);
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extern char &SIFixSGPRCopiesID;
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void initializeSIFixVGPRCopiesPass(PassRegistry &);
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extern char &SIFixVGPRCopiesID;
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void initializeSILowerI1CopiesPass(PassRegistry &);
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extern char &SILowerI1CopiesID;
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void initializeSILoadStoreOptimizerPass(PassRegistry &);
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extern char &SILoadStoreOptimizerID;
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void initializeSIWholeQuadModePass(PassRegistry &);
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extern char &SIWholeQuadModeID;
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void initializeSILowerControlFlowPass(PassRegistry &);
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extern char &SILowerControlFlowID;
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void initializeSIInsertSkipsPass(PassRegistry &);
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extern char &SIInsertSkipsPassID;
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void initializeSIOptimizeExecMaskingPass(PassRegistry &);
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extern char &SIOptimizeExecMaskingID;
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void initializeSIFixWWMLivenessPass(PassRegistry &);
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extern char &SIFixWWMLivenessID;
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void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &);
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extern char &AMDGPUSimplifyLibCallsID;
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void initializeAMDGPUUseNativeCallsPass(PassRegistry &);
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extern char &AMDGPUUseNativeCallsID;
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void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &);
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extern char &AMDGPUPerfHintAnalysisID;
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// Passes common to R600 and SI
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FunctionPass *createAMDGPUPromoteAlloca();
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void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
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extern char &AMDGPUPromoteAllocaID;
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Pass *createAMDGPUStructurizeCFGPass();
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FunctionPass *createAMDGPUISelDag(
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TargetMachine *TM = nullptr,
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CodeGenOpt::Level OptLevel = CodeGenOpt::Default);
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ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
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ModulePass *createR600OpenCLImageTypeLoweringPass();
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FunctionPass *createAMDGPUAnnotateUniformValues();
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ModulePass* createAMDGPUUnifyMetadataPass();
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void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
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extern char &AMDGPUUnifyMetadataID;
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void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&);
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extern char &SIOptimizeExecMaskingPreRAID;
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void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&);
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extern char &AMDGPUAnnotateUniformValuesPassID;
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void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
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extern char &AMDGPUCodeGenPrepareID;
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void initializeSIAnnotateControlFlowPass(PassRegistry&);
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extern char &SIAnnotateControlFlowPassID;
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void initializeSIMemoryLegalizerPass(PassRegistry&);
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extern char &SIMemoryLegalizerID;
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void initializeSIDebuggerInsertNopsPass(PassRegistry&);
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extern char &SIDebuggerInsertNopsID;
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void initializeSIInsertWaitcntsPass(PassRegistry&);
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extern char &SIInsertWaitcntsID;
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void initializeSIFormMemoryClausesPass(PassRegistry&);
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extern char &SIFormMemoryClausesID;
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void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&);
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extern char &AMDGPUUnifyDivergentExitNodesID;
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ImmutablePass *createAMDGPUAAWrapperPass();
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void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
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void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &);
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Pass *createAMDGPUFunctionInliningPass();
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void initializeAMDGPUInlinerPass(PassRegistry&);
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ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass();
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void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &);
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extern char &AMDGPUOpenCLEnqueuedBlockLoweringID;
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Target &getTheAMDGPUTarget();
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Target &getTheGCNTarget();
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namespace AMDGPU {
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enum TargetIndex {
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TI_CONSTDATA_START,
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TI_SCRATCH_RSRC_DWORD0,
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TI_SCRATCH_RSRC_DWORD1,
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TI_SCRATCH_RSRC_DWORD2,
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TI_SCRATCH_RSRC_DWORD3
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};
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}
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} // End namespace llvm
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/// OpenCL uses address spaces to differentiate between
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/// various memory regions on the hardware. On the CPU
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/// all of the address spaces point to the same memory,
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/// however on the GPU, each address space points to
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/// a separate piece of memory that is unique from other
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/// memory locations.
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struct AMDGPUAS {
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// The following address space values depend on the triple environment.
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unsigned PRIVATE_ADDRESS; ///< Address space for private memory.
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unsigned FLAT_ADDRESS; ///< Address space for flat memory.
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unsigned REGION_ADDRESS; ///< Address space for region memory.
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enum : unsigned {
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// The maximum value for flat, generic, local, private, constant and region.
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MAX_COMMON_ADDRESS = 5,
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GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
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CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2)
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LOCAL_ADDRESS = 3, ///< Address space for local memory.
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CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory
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/// Address space for direct addressible parameter memory (CONST0)
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PARAM_D_ADDRESS = 6,
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/// Address space for indirect addressible parameter memory (VTX1)
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PARAM_I_ADDRESS = 7,
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// Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on
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// this order to be able to dynamically index a constant buffer, for
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// example:
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//
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// ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
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CONSTANT_BUFFER_0 = 8,
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CONSTANT_BUFFER_1 = 9,
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CONSTANT_BUFFER_2 = 10,
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CONSTANT_BUFFER_3 = 11,
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CONSTANT_BUFFER_4 = 12,
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CONSTANT_BUFFER_5 = 13,
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CONSTANT_BUFFER_6 = 14,
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CONSTANT_BUFFER_7 = 15,
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CONSTANT_BUFFER_8 = 16,
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CONSTANT_BUFFER_9 = 17,
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CONSTANT_BUFFER_10 = 18,
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CONSTANT_BUFFER_11 = 19,
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CONSTANT_BUFFER_12 = 20,
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CONSTANT_BUFFER_13 = 21,
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CONSTANT_BUFFER_14 = 22,
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CONSTANT_BUFFER_15 = 23,
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// Some places use this if the address space can't be determined.
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UNKNOWN_ADDRESS_SPACE = ~0u,
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};
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};
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namespace llvm {
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namespace AMDGPU {
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AMDGPUAS getAMDGPUAS(const Module &M);
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AMDGPUAS getAMDGPUAS(const TargetMachine &TM);
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AMDGPUAS getAMDGPUAS(Triple T);
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} // namespace AMDGPU
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} // namespace llvm
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#endif
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