forked from OSchip/llvm-project
187 lines
6.1 KiB
LLVM
187 lines
6.1 KiB
LLVM
; REQUIRES: asserts
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; RUN: opt -S -dfa-jump-threading -debug-only=dfa-jump-threading -disable-output %s 2>&1 | FileCheck %s
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; This test checks that the analysis identifies all threadable paths in a
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; simple CFG. A threadable path includes a list of basic blocks, the exit
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; state, and the block that determines the next state.
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; < path of BBs that form a cycle > [ state, determinator ]
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define i32 @test1(i32 %num) {
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; CHECK: < for.body for.inc > [ 1, for.inc ]
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; CHECK-NEXT: < for.body case1 for.inc > [ 2, for.inc ]
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; CHECK-NEXT: < for.body case2 for.inc > [ 1, for.inc ]
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; CHECK-NEXT: < for.body case2 si.unfold.false for.inc > [ 2, for.inc ]
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entry:
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br label %for.body
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for.body:
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%count = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
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%state = phi i32 [ 1, %entry ], [ %state.next, %for.inc ]
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switch i32 %state, label %for.inc [
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i32 1, label %case1
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i32 2, label %case2
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]
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case1:
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br label %for.inc
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case2:
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%cmp = icmp eq i32 %count, 50
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%sel = select i1 %cmp, i32 1, i32 2
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br label %for.inc
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for.inc:
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%state.next = phi i32 [ %sel, %case2 ], [ 1, %for.body ], [ 2, %case1 ]
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%inc = add nsw i32 %count, 1
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%cmp.exit = icmp slt i32 %inc, %num
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br i1 %cmp.exit, label %for.body, label %for.end
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for.end:
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ret i32 0
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}
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; This test checks that the analysis finds threadable paths in a more
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; complicated CFG. Here the FSM is represented as a nested loop, with
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; fallthrough cases.
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define i32 @test2(i32 %init) {
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; CHECK: < loop.3 case2 > [ 3, loop.3 ]
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; CHECK-NEXT: < loop.3 case2 loop.1.backedge loop.1 loop.2 > [ 1, loop.1 ]
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; CHECK-NEXT: < loop.3 case2 loop.1.backedge si.unfold.false loop.1 loop.2 > [ 4, loop.1.backedge ]
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; CHECK-NEXT: < loop.3 case3 loop.2.backedge loop.2 > [ 0, loop.2.backedge ]
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; CHECK-NEXT: < loop.3 case3 case4 loop.2.backedge loop.2 > [ 3, loop.2.backedge ]
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; CHECK-NEXT: < loop.3 case3 case4 loop.1.backedge loop.1 loop.2 > [ 1, loop.1 ]
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; CHECK-NEXT: < loop.3 case3 case4 loop.1.backedge si.unfold.false loop.1 loop.2 > [ 2, loop.1.backedge ]
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; CHECK-NEXT: < loop.3 case4 loop.2.backedge loop.2 > [ 3, loop.2.backedge ]
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; CHECK-NEXT: < loop.3 case4 loop.1.backedge loop.1 loop.2 > [ 1, loop.1 ]
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; CHECK-NEXT: < loop.3 case4 loop.1.backedge si.unfold.false loop.1 loop.2 > [ 2, loop.1.backedge ]
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entry:
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%cmp = icmp eq i32 %init, 0
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%sel = select i1 %cmp, i32 0, i32 2
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br label %loop.1
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loop.1:
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%state.1 = phi i32 [ %sel, %entry ], [ %state.1.be2, %loop.1.backedge ]
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br label %loop.2
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loop.2:
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%state.2 = phi i32 [ %state.1, %loop.1 ], [ %state.2.be, %loop.2.backedge ]
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br label %loop.3
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loop.3:
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%state = phi i32 [ %state.2, %loop.2 ], [ 3, %case2 ]
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switch i32 %state, label %infloop.i [
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i32 2, label %case2
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i32 3, label %case3
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i32 4, label %case4
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i32 0, label %case0
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i32 1, label %case1
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]
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case2:
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br i1 %cmp, label %loop.3, label %loop.1.backedge
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case3:
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br i1 %cmp, label %loop.2.backedge, label %case4
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case4:
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br i1 %cmp, label %loop.2.backedge, label %loop.1.backedge
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loop.1.backedge:
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%state.1.be = phi i32 [ 2, %case4 ], [ 4, %case2 ]
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%state.1.be2 = select i1 %cmp, i32 1, i32 %state.1.be
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br label %loop.1
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loop.2.backedge:
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%state.2.be = phi i32 [ 3, %case4 ], [ 0, %case3 ]
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br label %loop.2
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case0:
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br label %exit
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case1:
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br label %exit
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infloop.i:
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br label %infloop.i
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exit:
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ret i32 0
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}
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declare void @baz()
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; Do not jump-thread those paths where the determinator basic block does not
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; precede the basic block that defines the switch condition.
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;
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; Otherwise, it is possible that the state defined in the determinator block
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; defines the state for the next iteration of the loop, rather than for the
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; current one.
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define i32 @wrong_bb_order() {
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; CHECK-LABEL: DFA Jump threading: wrong_bb_order
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; CHECK-NOT: < bb43 bb59 bb3 bb31 bb41 > [ 77, bb43 ]
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; CHECK-NOT: < bb43 bb49 bb59 bb3 bb31 bb41 > [ 77, bb43 ]
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bb:
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%i = alloca [420 x i8], align 1
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%i2 = getelementptr inbounds [420 x i8], [420 x i8]* %i, i64 0, i64 390
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br label %bb3
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bb3: ; preds = %bb59, %bb
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%i4 = phi i8* [ %i2, %bb ], [ %i60, %bb59 ]
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%i5 = phi i8 [ 77, %bb ], [ %i64, %bb59 ]
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%i6 = phi i32 [ 2, %bb ], [ %i63, %bb59 ]
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%i7 = phi i32 [ 26, %bb ], [ %i62, %bb59 ]
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%i8 = phi i32 [ 25, %bb ], [ %i61, %bb59 ]
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%i9 = icmp sgt i32 %i7, 2
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%i10 = select i1 %i9, i32 %i7, i32 2
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%i11 = add i32 %i8, 2
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%i12 = sub i32 %i11, %i10
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%i13 = mul nsw i32 %i12, 3
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%i14 = add nsw i32 %i13, %i6
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%i15 = sext i32 %i14 to i64
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%i16 = getelementptr inbounds i8, i8* %i4, i64 %i15
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%i17 = load i8, i8* %i16, align 1
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%i18 = icmp sgt i8 %i17, 0
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br i1 %i18, label %bb21, label %bb31
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bb21: ; preds = %bb3
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br i1 true, label %bb59, label %bb43
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bb59: ; preds = %bb49, %bb43, %bb31, %bb21
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%i60 = phi i8* [ %i44, %bb49 ], [ %i44, %bb43 ], [ %i34, %bb31 ], [ %i4, %bb21 ]
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%i61 = phi i32 [ %i45, %bb49 ], [ %i45, %bb43 ], [ %i33, %bb31 ], [ %i8, %bb21 ]
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%i62 = phi i32 [ %i47, %bb49 ], [ %i47, %bb43 ], [ %i32, %bb31 ], [ %i7, %bb21 ]
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%i63 = phi i32 [ %i48, %bb49 ], [ %i48, %bb43 ], [ 2, %bb31 ], [ %i6, %bb21 ]
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%i64 = phi i8 [ %i46, %bb49 ], [ %i46, %bb43 ], [ 77, %bb31 ], [ %i5, %bb21 ]
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%i65 = icmp sgt i32 %i62, 0
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br i1 %i65, label %bb3, label %bb66
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bb31: ; preds = %bb3
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%i32 = add nsw i32 %i7, -1
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%i33 = add nsw i32 %i8, -1
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%i34 = getelementptr inbounds i8, i8* %i4, i64 -15
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%i35 = icmp eq i8 %i5, 77
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br i1 %i35, label %bb59, label %bb41
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bb41: ; preds = %bb31
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tail call void @baz()
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br label %bb43
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bb43: ; preds = %bb41, %bb21
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%i44 = phi i8* [ %i34, %bb41 ], [ %i4, %bb21 ]
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%i45 = phi i32 [ %i33, %bb41 ], [ %i8, %bb21 ]
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%i46 = phi i8 [ 77, %bb41 ], [ %i5, %bb21 ]
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%i47 = phi i32 [ %i32, %bb41 ], [ %i7, %bb21 ]
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%i48 = phi i32 [ 2, %bb41 ], [ %i6, %bb21 ]
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tail call void @baz()
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switch i8 %i5, label %bb59 [
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i8 68, label %bb49
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i8 73, label %bb49
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]
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bb49: ; preds = %bb43, %bb43
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tail call void @baz()
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br label %bb59
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bb66: ; preds = %bb59
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ret i32 0
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}
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