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Sebastian Pop c33af715d7 [AArch64] generate vuzp instead of mov 
when a BUILD_VECTOR is created out of a sequence of EXTRACT_VECTOR_ELT with a
specific pattern sequence, either <0, 2, 4, ...> or <1, 3, 5, ...>, replace the
BUILD_VECTOR with either vuzp1 or vuzp2.

With this patch LLVM generates the following code for the first function fun1 in the testcase:
adrp x8, .LCPI0_0
ldr  q0, [x8, :lo12:.LCPI0_0]
tbl  v0.16b, { v0.16b }, v0.16b
ext  v1.16b, v0.16b, v0.16b, #8
uzp1 v0.8b, v0.8b, v1.8b
str  d0, [x8]
ret

Without this patch LLVM currently generates this code:
adrp    x8, .LCPI0_0
ldr     q0, [x8, :lo12:.LCPI0_0]
tbl     v0.16b, { v0.16b }, v0.16b
mov     v1.16b, v0.16b
mov     v1.b[1], v0.b[2]
mov     v1.b[2], v0.b[4]
mov     v1.b[3], v0.b[6]
mov     v1.b[4], v0.b[8]
mov     v1.b[5], v0.b[10]
mov     v1.b[6], v0.b[12]
mov     v1.b[7], v0.b[14]
str     d1, [x8]
ret

llvm-svn: 326443
 		2018-03-01 15:47:39 +00:00
..
AsmParser [AArch64][AsmParser] NFC: Generalize LogicalImm[Not](32|64) code 2018-01-29 13:05:38 +00:00
Disassembler [AArch64][SVE] Asm: Add AND_ZI instructions and aliases 2018-02-06 13:13:21 +00:00
InstPrinter [AArch64][AsmParser] NFC: Generalize LogicalImm[Not](32|64) code 2018-01-29 13:05:38 +00:00
MCTargetDesc [AArch64][SVE] Asm: Add AND_ZI instructions and aliases 2018-02-06 13:13:21 +00:00
TargetInfo Add backend name to Target to enable runtime info to be fed back into TableGen 2017-11-15 23:55:44 +00:00
Utils [AArch64][SVE] Asm: Predicate patterns 2018-01-22 10:46:00 +00:00
AArch64.h [AArch64] Avoid SIMD interleaved store instruction for Exynos. 2017-12-08 00:58:49 +00:00
AArch64.td [PATCH] [AArch64] Add new target feature to fuse conditional select 2018-02-23 19:27:43 +00:00
AArch64A53Fix835769.cpp Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 2017-11-08 01:01:31 +00:00
AArch64A57FPLoadBalancing.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64AdvSIMDScalarPass.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64AsmPrinter.cpp [CodeGen] Hoist common AsmPrinter code out of X86, ARM, and AArch64 2018-01-17 23:55:23 +00:00
AArch64CallLowering.cpp [GISel]: Don't assert when constraining RegisterOperands which are uses. 2018-02-26 22:56:21 +00:00
AArch64CallLowering.h GlobalISel (AArch64): fix ABI at border between GPRs and SP. 2017-08-21 21:56:11 +00:00
AArch64CallingConvention.h Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 2017-11-08 01:01:31 +00:00
AArch64CallingConvention.td [AArch64] Implement dynamic stack probing for windows 2018-02-17 14:26:32 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64CollectLOH.cpp Revert "[CodeGen] Move printing '\n' from MachineInstr::print to MachineBasicBlock::print" 2018-02-19 15:08:49 +00:00
AArch64CondBrTuning.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64ConditionOptimizer.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64ConditionalCompares.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64DeadRegisterDefinitionsPass.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64ExpandPseudoInsts.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
AArch64FalkorHWPFFix.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64FastISel.cpp [AArch64FastISel] Replace deprecated calls to MemoryIntrinsic::getAlignment() (NFCI) 2018-02-09 21:49:29 +00:00
AArch64FrameLowering.cpp Support for the mno-stack-arg-probe flag 2018-02-23 13:46:25 +00:00
AArch64FrameLowering.h Move TargetFrameLowering.h to CodeGen where it's implemented 2017-11-03 22:32:11 +00:00
AArch64GenRegisterBankInfo.def [AArch64][RegisterBankInfo] Teach instruction mapping about gpr32 -> fpr16 cross copies 2017-11-18 04:28:56 +00:00
AArch64ISelDAGToDAG.cpp [AArch64] Coalesce Copy Zero during instruction selection 2018-02-18 13:51:33 +00:00
AArch64ISelLowering.cpp [AArch64] generate vuzp instead of mov 2018-03-01 15:47:39 +00:00
AArch64ISelLowering.h [AArch64] Implement dynamic stack probing for windows 2018-02-17 14:26:32 +00:00
AArch64InstrAtomics.td [AArch64] Improve v8.1-A code-gen for atomic load-and 2018-02-12 17:03:11 +00:00
AArch64InstrFormats.td [AArch64][AsmParser] NFC: Generalize LogicalImm[Not](32|64) code 2018-01-29 13:05:38 +00:00
AArch64InstrInfo.cpp [AArch64] Refactor stand alone methods (NFC) 2018-02-09 16:14:41 +00:00
AArch64InstrInfo.h [AArch64] Refactor stand alone methods (NFC) 2018-02-09 16:14:41 +00:00
AArch64InstrInfo.td [AArch64] Fixes for ARMv8.2-A FP16 scalar intrinsic - llvm portion 2018-02-12 17:35:42 +00:00
AArch64InstructionSelector.cpp [AArch64][GlobalISel] When copying from a gpr32 to an fpr16 reg, convert to fpr32 first. 2018-02-20 05:11:57 +00:00
AArch64LegalizerInfo.cpp [globalisel][legalizerinfo] Follow up on post-commit review comments after r323681 2018-02-13 23:02:44 +00:00
AArch64LegalizerInfo.h [aarch64][globalisel] Define G_ATOMIC_CMPXCHG and G_ATOMICRMW_* and make them legal 2017-11-28 20:21:15 +00:00
AArch64LoadStoreOptimizer.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64MCInstLower.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
AArch64MCInstLower.h [COFF, ARM64] Add support for Windows ARM64 COFF format 2017-06-27 23:58:19 +00:00
AArch64MachineFunctionInfo.h [AArch64] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-07-25 23:51:02 +00:00
AArch64MacroFusion.cpp [PATCH] [AArch64] Add new target feature to fuse conditional select 2018-02-23 19:27:43 +00:00
AArch64MacroFusion.h Recommit rL305677: [CodeGen] Add generic MacroFusion pass 2017-06-19 12:53:31 +00:00
AArch64PBQPRegAlloc.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
AArch64PBQPRegAlloc.h [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-06-01 23:25:02 +00:00
AArch64PerfectShuffle.h
…
AArch64PromoteConstant.cpp [AArch64] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-07-25 23:51:02 +00:00
AArch64RedundantCopyElimination.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64RegisterBankInfo.cpp [AArch64] Map G_LOAD on FPR when the definition goes to a copy to FPR 2017-11-18 04:28:59 +00:00
AArch64RegisterBankInfo.h [AArch64][RegisterBankInfo] Add mapping for G_FPEXT. 2017-11-02 23:38:19 +00:00
AArch64RegisterBanks.td [aarch64][globalisel] Register banks and classes should have distinct names. 2017-10-18 00:12:43 +00:00
AArch64RegisterInfo.cpp [AArch64] Implement dynamic stack probing for windows 2018-02-17 14:26:32 +00:00
AArch64RegisterInfo.h [AArch64] Implement dynamic stack probing for windows 2018-02-17 14:26:32 +00:00
AArch64RegisterInfo.td [AArch64][SVE] Asm: Add restricted register classes for SVE predicate vectors. 2018-01-03 10:15:46 +00:00
AArch64SIMDInstrOpt.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64SVEInstrInfo.td [AArch64][SVE] Asm: Add AND_ZI instructions and aliases 2018-02-06 13:13:21 +00:00
AArch64SchedA53.td [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models. 2017-11-07 15:03:11 +00:00
AArch64SchedA57.td [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models. 2017-11-07 15:03:11 +00:00
AArch64SchedA57WriteRes.td
…
AArch64SchedCyclone.td [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models. 2017-11-07 15:03:11 +00:00
AArch64SchedExynosM1.td [AArch64][NFC] Make all ProcResource definitions include their SchedModel. 2018-02-01 12:12:01 +00:00
AArch64SchedExynosM3.td [AArch64] Adjust the cost model for Exynos M3 2018-02-09 19:26:11 +00:00
AArch64SchedFalkor.td [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models. 2017-11-07 15:03:11 +00:00
AArch64SchedFalkorDetails.td [AArch64][Falkor] Remove some non-existent opcodes from sched detail regexes. NFC. 2017-06-23 21:59:09 +00:00
AArch64SchedKryo.td [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models. 2017-11-07 15:03:11 +00:00
AArch64SchedKryoDetails.td [AArch64][Kryo] Add missing write latency for LDAXP, LDXP second destination. 2017-06-19 21:57:42 +00:00
AArch64SchedThunderX.td [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models. 2017-11-07 15:03:11 +00:00
AArch64SchedThunderX2T99.td [AArch64][NFC] Make all ProcResource definitions include their SchedModel. 2018-02-01 12:12:01 +00:00
AArch64Schedule.td
…
AArch64SelectionDAGInfo.cpp AArch64/X86: Factor out common bzero logic; NFC 2017-12-18 23:14:28 +00:00
AArch64SelectionDAGInfo.h
…
AArch64StorePairSuppress.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64Subtarget.cpp [AArch64] Properly handle dllimport of variables when using fast-isel 2018-01-30 19:50:51 +00:00
AArch64Subtarget.h [PATCH] [AArch64] Add new target feature to fuse conditional select 2018-02-23 19:27:43 +00:00
AArch64SystemOperands.td [AArch64] Fix spelling of ICH_ELRSR_EL2 system register 2018-02-06 09:39:04 +00:00
AArch64TargetMachine.cpp Add a TargetOption to enable/disable GlobalISel 2018-01-17 22:34:21 +00:00
AArch64TargetMachine.h (Re-landing) Expose a TargetMachine::getTargetTransformInfo function 2017-12-22 18:21:59 +00:00
AArch64TargetObjectFile.cpp Move Object format code to lib/BinaryFormat. 2017-06-07 03:48:56 +00:00
AArch64TargetObjectFile.h Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
AArch64TargetTransformInfo.cpp Fix -Wsign-compare warnings on Windows 2018-01-05 19:53:51 +00:00
AArch64TargetTransformInfo.h [AArch64] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-07-25 23:51:02 +00:00
CMakeLists.txt [AArch64] Rename AArch64VecorByElementOpt.cpp into AArch64SIMDInstrOpt.cpp to reflect the recently added features. 2017-12-08 22:04:13 +00:00
LLVMBuild.txt
…
SVEInstrFormats.td [AArch64][SVE] Asm: Add AND_ZI instructions and aliases 2018-02-06 13:13:21 +00:00