forked from OSchip/llvm-project
ca999f7191
The execution mode of a kernel is stored in a global variable, whose value means: - 0 - SPMD mode - 1 - indicates generic mode - 2 - SPMD mode execution with generic mode semantics We are going to add support for SIMD execution mode. It will be come with another execution mode, such as SIMD-generic mode. As a result, this value-based indicator is not flexible. This patch changes to bitset based solution to encode execution mode. Each position is: [0] - generic mode [1] - SPMD mode [2] - SIMD mode (will be added later) In this way, `0x1` is generic mode, `0x2` is SPMD mode, and `0x3` is SPMD mode execution with generic mode semantics. In the future after we add the support for SIMD mode, `0b1xx` will be in SIMD mode. Reviewed By: jdoerfert Differential Revision: https://reviews.llvm.org/D110029 |
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| .. | ||
| aarch64 | ||
| amdgpu | ||
| common | ||
| cuda | ||
| generic-elf-64bit/src | ||
| ppc64 | ||
| ppc64le | ||
| remote | ||
| ve | ||
| x86_64 | ||
| CMakeLists.txt | ||
| exports | ||