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llvm-project/llvm/lib/Target/RISCV/MCTargetDesc
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Sameer AbuAsal c1b0e66b58 [RISCV] Tablegen-driven Instruction Compression. 
Summary:

    This patch implements a tablegen-driven Instruction Compression
    mechanism for generating RISCV compressed instructions
    (C Extension) from the expanded instruction form.

    This tablegen backend processes CompressPat declarations in a
    td file and generates all the compile-time and runtime checks
    required to validate the declarations, validate the input
    operands and generate correct instructions.

    The checks include validating register operands, immediate
    operands, fixed register operands and fixed immediate operands.

    Example:
      class CompressPat<dag input, dag output> {
        dag Input  = input;
        dag Output    = output;
        list<Predicate> Predicates = [];
      }

      let Predicates = [HasStdExtC] in {
      def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),
                        (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
      }

    The result is an auto-generated header file
    'RISCVGenCompressEmitter.inc' which exports two functions for
    compressing/uncompressing MCInst instructions, plus
    some helper functions:

      bool compressInst(MCInst& OutInst, const MCInst &MI,
                        const MCSubtargetInfo &STI,
                        MCContext &Context);

      bool uncompressInst(MCInst& OutInst, const MCInst &MI,
                          const MCRegisterInfo &MRI,
                          const MCSubtargetInfo &STI);

    The clients that include this auto-generated header file and
    invoke these functions can compress an instruction before emitting
    it, in the target-specific ASM or ELF streamer, or can uncompress
    an instruction before printing it, when the expanded instruction
    format aliases is favored.

    The following clients were added to implement compression\uncompression
    for RISCV:

    1) RISCVAsmParser::MatchAndEmitInstruction:
       Inserted a call to compressInst() to compresses instructions
       parsed by llvm-mc coming from an ASM input.
    2) RISCVAsmPrinter::EmitInstruction:
       Inserted a call to compressInst() to compress instructions that
       were lowered from Machine Instructions (MachineInstr).
    3) RVInstPrinter::printInst:
       Inserted a call to uncompressInst() to print the expanded
       version of the instruction instead of the compressed one (e.g,
       add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases
       is not passed.

This patch squashes D45119, D42780 and D41932. It was reviewed in  smaller patches by
asb, efriedma, apazos and mgrang.

Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal

Reviewed By: sabuasal

Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng

Differential Revision: https://reviews.llvm.org/D45385

llvm-svn: 329455
 		2018-04-06 21:07:05 +00:00
..
CMakeLists.txt [RISCV] Encode RISCV specific ELF e_flags to RISCV Binary by RISCVTargetStreamer 2018-01-26 07:53:07 +00:00
LLVMBuild.txt [RISCV] Add RISCVInstPrinter and basic MC assembler tests 2017-08-15 13:08:29 +00:00
RISCVAsmBackend.cpp [RISCV] Implement MC relaxations for compressed instructions. 2018-03-02 22:04:12 +00:00
RISCVBaseInfo.h [RISCV] MC layer support for load/store instructions of the C (compressed) extension 2017-12-07 12:50:32 +00:00
RISCVELFObjectWriter.cpp [RISCV] Add support for %pcrel_lo. 2018-02-06 00:55:23 +00:00
RISCVELFStreamer.cpp [RISCV] Encode RISCV specific ELF e_flags to RISCV Binary by RISCVTargetStreamer 2018-01-26 07:53:07 +00:00
RISCVELFStreamer.h [RISCV] Encode RISCV specific ELF e_flags to RISCV Binary by RISCVTargetStreamer 2018-01-26 07:53:07 +00:00
RISCVFixupKinds.h [RISCV] Add support for %pcrel_lo. 2018-02-06 00:55:23 +00:00
RISCVMCAsmInfo.cpp Distinguish between code pointer size and DataLayout::getPointerSize() in DWARF info generation 2017-04-17 17:41:25 +00:00
RISCVMCAsmInfo.h
…
RISCVMCCodeEmitter.cpp [RISCV][NFC] Make logic in RISCVMCCodeEmitter::getImmOpValue more defensive 2018-02-22 13:24:25 +00:00
RISCVMCExpr.cpp [RISCV] Tablegen-driven Instruction Compression. 2018-04-06 21:07:05 +00:00
RISCVMCExpr.h [RISCV] Tablegen-driven Instruction Compression. 2018-04-06 21:07:05 +00:00
RISCVMCTargetDesc.cpp [RISCV] Encode RISCV specific ELF e_flags to RISCV Binary by RISCVTargetStreamer 2018-01-26 07:53:07 +00:00
RISCVMCTargetDesc.h Thread MCSubtargetInfo through Target::createMCAsmBackend 2018-01-03 08:53:05 +00:00
RISCVTargetStreamer.cpp [RISCV] Encode RISCV specific ELF e_flags to RISCV Binary by RISCVTargetStreamer 2018-01-26 07:53:07 +00:00
RISCVTargetStreamer.h [RISCV] Encode RISCV specific ELF e_flags to RISCV Binary by RISCVTargetStreamer 2018-01-26 07:53:07 +00:00