forked from OSchip/llvm-project
1084 lines
32 KiB
TableGen
1084 lines
32 KiB
TableGen
//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===------------------------------------------------------------===//
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include "llvm/TableGen/SearchableTable.td"
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include "llvm/Target/Target.td"
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include "AMDGPUFeatures.td"
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class BoolToList<bit Value> {
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list<int> ret = !if(Value, [1]<int>, []<int>);
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}
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//===------------------------------------------------------------===//
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// Subtarget Features (device properties)
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//===------------------------------------------------------------===//
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def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
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"FastFMAF32",
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"true",
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"Assuming f32 fma is at least as fast as mul + add"
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>;
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def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
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"MIMG_R128",
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"true",
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"Support 128-bit texture resources"
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>;
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def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
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"HalfRate64Ops",
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"true",
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"Most fp64 instructions are half rate instead of quarter"
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>;
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def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
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"FlatAddressSpace",
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"true",
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"Support flat address space"
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>;
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def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
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"FlatInstOffsets",
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"true",
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"Flat instructions have immediate offset addressing mode"
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>;
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def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
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"FlatGlobalInsts",
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"true",
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"Have global_* flat memory instructions"
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>;
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def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
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"FlatScratchInsts",
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"true",
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"Have scratch_* flat memory instructions"
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>;
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def FeatureScalarFlatScratchInsts : SubtargetFeature<"scalar-flat-scratch-insts",
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"ScalarFlatScratchInsts",
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"true",
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"Have s_scratch_* flat memory instructions"
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>;
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def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
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"AddNoCarryInsts",
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"true",
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"Have VALU add/sub instructions without carry out"
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>;
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def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
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"UnalignedBufferAccess",
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"true",
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"Support unaligned global loads and stores"
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>;
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def FeatureTrapHandler: SubtargetFeature<"trap-handler",
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"TrapHandler",
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"true",
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"Trap handler support"
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>;
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def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
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"UnalignedScratchAccess",
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"true",
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"Support unaligned scratch loads and stores"
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>;
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def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
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"HasApertureRegs",
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"true",
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"Has Memory Aperture Base and Size Registers"
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>;
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def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
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"HasMadMixInsts",
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"true",
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"Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
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>;
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def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
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"HasFmaMixInsts",
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"true",
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"Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
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>;
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def FeatureDoesNotSupportXNACK : SubtargetFeature<"no-xnack-support",
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"DoesNotSupportXNACK",
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"true",
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"Hardware does not support XNACK"
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>;
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// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
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// XNACK. The current default kernel driver setting is:
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// - graphics ring: XNACK disabled
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// - compute ring: XNACK enabled
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//
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// If XNACK is enabled, the VMEM latency can be worse.
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// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
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def FeatureXNACK : SubtargetFeature<"xnack",
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"EnableXNACK",
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"true",
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"Enable XNACK support"
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>;
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def FeatureCuMode : SubtargetFeature<"cumode",
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"EnableCuMode",
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"true",
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"Enable CU wavefront execution mode"
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>;
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def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
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"SGPRInitBug",
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"true",
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"VI SGPR initialization bug requiring a fixed SGPR allocation size"
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>;
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def FeatureLdsMisalignedBug : SubtargetFeature<"lds-misaligned-bug",
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"LDSMisalignedBug",
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"true",
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"Some GFX10 bug with misaligned multi-dword LDS access in WGP mode"
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>;
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def FeatureVcmpxPermlaneHazard : SubtargetFeature<"vcmpx-permlane-hazard",
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"HasVcmpxPermlaneHazard",
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"true",
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"TODO: describe me"
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>;
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def FeatureVMEMtoScalarWriteHazard : SubtargetFeature<"vmem-to-scalar-write-hazard",
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"HasVMEMtoScalarWriteHazard",
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"true",
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"VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution."
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>;
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def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
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"HasSMEMtoVectorWriteHazard",
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"true",
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"s_load_dword followed by v_cmp page faults"
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>;
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def FeatureInstFwdPrefetchBug : SubtargetFeature<"inst-fwd-prefetch-bug",
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"HasInstFwdPrefetchBug",
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"true",
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"S_INST_PREFETCH instruction causes shader to hang"
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>;
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def FeatureVcmpxExecWARHazard : SubtargetFeature<"vcmpx-exec-war-hazard",
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"HasVcmpxExecWARHazard",
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"true",
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"V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)"
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>;
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def FeatureLdsBranchVmemWARHazard : SubtargetFeature<"lds-branch-vmem-war-hazard",
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"HasLdsBranchVmemWARHazard",
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"true",
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"Switching between LDS and VMEM-tex not waiting VM_VSRC=0"
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>;
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def FeatureNSAtoVMEMBug : SubtargetFeature<"nsa-to-vmem-bug",
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"HasNSAtoVMEMBug",
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"true",
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"MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
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>;
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def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug",
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"HasFlatSegmentOffsetBug",
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"true",
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"GFX10 bug, inst_offset ignored in flat segment"
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>;
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class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
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"ldsbankcount"#Value,
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"LDSBankCount",
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!cast<string>(Value),
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"The number of LDS banks per compute unit."
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>;
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def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
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def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
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def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
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"GCN3Encoding",
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"true",
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"Encoding format for VI"
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>;
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def FeatureCIInsts : SubtargetFeature<"ci-insts",
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"CIInsts",
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"true",
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"Additional instructions for CI+"
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>;
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def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts",
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"GFX8Insts",
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"true",
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"Additional instructions for GFX8+"
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>;
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def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
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"GFX9Insts",
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"true",
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"Additional instructions for GFX9+"
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>;
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def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",
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"GFX10Insts",
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"true",
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"Additional instructions for GFX10+"
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>;
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def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts",
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"GFX7GFX8GFX9Insts",
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"true",
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"Instructions shared in GFX7, GFX8, GFX9"
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>;
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def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
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"HasSMemRealTime",
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"true",
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"Has s_memrealtime instruction"
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>;
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def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
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"HasInv2PiInlineImm",
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"true",
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"Has 1 / (2 * pi) as inline immediate"
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>;
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def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
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"Has16BitInsts",
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"true",
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"Has i16/f16 instructions"
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>;
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def FeatureVOP3P : SubtargetFeature<"vop3p",
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"HasVOP3PInsts",
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"true",
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"Has VOP3P packed instructions"
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>;
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def FeatureMovrel : SubtargetFeature<"movrel",
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"HasMovrel",
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"true",
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"Has v_movrel*_b32 instructions"
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>;
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def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
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"HasVGPRIndexMode",
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"true",
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"Has VGPR mode register indexing"
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>;
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def FeatureScalarStores : SubtargetFeature<"scalar-stores",
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"HasScalarStores",
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"true",
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"Has store scalar memory instructions"
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>;
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def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
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"HasScalarAtomics",
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"true",
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"Has atomic scalar memory instructions"
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>;
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def FeatureSDWA : SubtargetFeature<"sdwa",
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"HasSDWA",
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"true",
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"Support SDWA (Sub-DWORD Addressing) extension"
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>;
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def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
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"HasSDWAOmod",
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"true",
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"Support OMod with SDWA (Sub-DWORD Addressing) extension"
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>;
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def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
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"HasSDWAScalar",
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"true",
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"Support scalar register with SDWA (Sub-DWORD Addressing) extension"
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>;
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def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
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"HasSDWASdst",
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"true",
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"Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
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>;
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def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
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"HasSDWAMac",
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"true",
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"Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
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>;
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def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
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"HasSDWAOutModsVOPC",
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"true",
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"Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
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>;
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def FeatureDPP : SubtargetFeature<"dpp",
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"HasDPP",
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"true",
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"Support DPP (Data Parallel Primitives) extension"
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>;
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// DPP8 allows arbitrary cross-lane swizzling withing groups of 8 lanes.
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def FeatureDPP8 : SubtargetFeature<"dpp8",
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"HasDPP8",
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"true",
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"Support DPP8 (Data Parallel Primitives) extension"
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>;
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def FeatureR128A16 : SubtargetFeature<"r128-a16",
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"HasR128A16",
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"true",
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"Support 16 bit coordindates/gradients/lod/clamp/mip types on gfx9"
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>;
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def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding",
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"HasNSAEncoding",
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"true",
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"Support NSA encoding for image instructions"
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>;
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def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
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"HasIntClamp",
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"true",
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"Support clamp for integer destination"
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>;
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def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
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"HasUnpackedD16VMem",
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"true",
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"Has unpacked d16 vmem instructions"
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>;
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def FeatureDLInsts : SubtargetFeature<"dl-insts",
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"HasDLInsts",
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"true",
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"Has v_fmac_f32 and v_xnor_b32 instructions"
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>;
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def FeatureDot1Insts : SubtargetFeature<"dot1-insts",
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"HasDot1Insts",
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"true",
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"Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions"
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>;
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def FeatureDot2Insts : SubtargetFeature<"dot2-insts",
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"HasDot2Insts",
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"true",
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"Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions"
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>;
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def FeatureDot5Insts : SubtargetFeature<"dot5-insts",
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"HasDot5Insts",
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"true",
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"Has v_dot2c_f32_f16 instruction"
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>;
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def FeatureDot6Insts : SubtargetFeature<"dot6-insts",
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"HasDot6Insts",
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"true",
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"Has v_dot4c_i32_i8 instruction"
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>;
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def FeatureDoesNotSupportSRAMECC : SubtargetFeature<"no-sram-ecc-support",
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"DoesNotSupportSRAMECC",
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"true",
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"Hardware does not support SRAM ECC"
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>;
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def FeatureSRAMECC : SubtargetFeature<"sram-ecc",
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"EnableSRAMECC",
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"true",
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"Enable SRAM ECC"
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>;
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def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
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"HasNoSdstCMPX",
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"true",
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"V_CMPX does not write VCC/SGPR in addition to EXEC"
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>;
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def FeatureVscnt : SubtargetFeature<"vscnt",
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"HasVscnt",
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"true",
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"Has separate store vscnt counter"
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>;
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def FeatureRegisterBanking : SubtargetFeature<"register-banking",
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"HasRegisterBanking",
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"true",
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"Has register banking"
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>;
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def FeatureVOP3Literal : SubtargetFeature<"vop3-literal",
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"HasVOP3Literal",
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"true",
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"Can use one literal in VOP3"
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>;
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def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard",
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"HasNoDataDepHazard",
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"true",
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"Does not need SW waitstates"
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>;
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//===------------------------------------------------------------===//
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// Subtarget Features (options and debugging)
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//===------------------------------------------------------------===//
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// Denormal handling for fp64 and fp16 is controlled by the same
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// config register when fp16 supported.
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// TODO: Do we need a separate f16 setting when not legal?
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def FeatureFP64FP16Denormals : SubtargetFeature<"fp64-fp16-denormals",
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"FP64FP16Denormals",
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"true",
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"Enable double and half precision denormal handling",
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[FeatureFP64]
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>;
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def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
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"FP64FP16Denormals",
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"true",
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"Enable double and half precision denormal handling",
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[FeatureFP64, FeatureFP64FP16Denormals]
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>;
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def FeatureFP16Denormals : SubtargetFeature<"fp16-denormals",
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"FP64FP16Denormals",
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"true",
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"Enable half precision denormal handling",
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[FeatureFP64FP16Denormals]
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>;
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def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
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"FPExceptions",
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"true",
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"Enable floating point exceptions"
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>;
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class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
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"max-private-element-size-"#size,
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"MaxPrivateElementSize",
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!cast<string>(size),
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"Maximum private access size may be "#size
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>;
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def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
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def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
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def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
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def FeatureDumpCode : SubtargetFeature <"DumpCode",
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"DumpCode",
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"true",
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"Dump MachineInstrs in the CodeEmitter"
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>;
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def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
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"DumpCode",
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"true",
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"Dump MachineInstrs in the CodeEmitter"
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>;
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// XXX - This should probably be removed once enabled by default
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def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
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"EnableLoadStoreOpt",
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"true",
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"Enable SI load/store optimizer pass"
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>;
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// Performance debugging feature. Allow using DS instruction immediate
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// offsets even if the base pointer can't be proven to be base. On SI,
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// base pointer values that won't give the same result as a 16-bit add
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// are not safe to fold, but this will override the conservative test
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// for the base pointer.
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def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
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"unsafe-ds-offset-folding",
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"EnableUnsafeDSOffsetFolding",
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"true",
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"Force using DS instruction immediate offsets on SI"
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>;
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def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
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"EnableSIScheduler",
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"true",
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"Enable SI Machine Scheduler"
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>;
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def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
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"EnableDS128",
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"true",
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"Use ds_{read|write}_b128"
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>;
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// Sparse texture support requires that all result registers are zeroed when
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// PRTStrictNull is set to true. This feature is turned on for all architectures
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// but is enabled as a feature in case there are situations where PRTStrictNull
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// is disabled by the driver.
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def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
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"EnablePRTStrictNull",
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"true",
|
|
"Enable zeroing of result registers for sparse texture fetches"
|
|
>;
|
|
|
|
// Unless +-flat-for-global is specified, turn on FlatForGlobal for
|
|
// all OS-es on VI and newer hardware to avoid assertion failures due
|
|
// to missing ADDR64 variants of MUBUF instructions.
|
|
// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
|
|
// instructions.
|
|
|
|
def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
|
|
"FlatForGlobal",
|
|
"true",
|
|
"Force to generate flat instruction for global"
|
|
>;
|
|
|
|
def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
|
|
"auto-waitcnt-before-barrier",
|
|
"AutoWaitcntBeforeBarrier",
|
|
"true",
|
|
"Hardware automatically inserts waitcnt before barrier"
|
|
>;
|
|
|
|
def FeatureCodeObjectV3 : SubtargetFeature <
|
|
"code-object-v3",
|
|
"CodeObjectV3",
|
|
"true",
|
|
"Generate code object version 3"
|
|
>;
|
|
|
|
def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
|
|
"HasTrigReducedRange",
|
|
"true",
|
|
"Requires use of fract on arguments to trig instructions"
|
|
>;
|
|
|
|
// Dummy feature used to disable assembler instructions.
|
|
def FeatureDisable : SubtargetFeature<"",
|
|
"FeatureDisable","true",
|
|
"Dummy feature to disable assembler instructions"
|
|
>;
|
|
|
|
class GCNSubtargetFeatureGeneration <string Value,
|
|
string FeatureName,
|
|
list<SubtargetFeature> Implies> :
|
|
SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
|
|
|
|
def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
|
|
"southern-islands",
|
|
[FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
|
|
FeatureWavefrontSize64,
|
|
FeatureLDSBankCount32, FeatureMovrel, FeatureTrigReducedRange,
|
|
FeatureDoesNotSupportSRAMECC, FeatureDoesNotSupportXNACK]
|
|
>;
|
|
|
|
def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
|
|
"sea-islands",
|
|
[FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
|
|
FeatureWavefrontSize64, FeatureFlatAddressSpace,
|
|
FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
|
|
FeatureGFX7GFX8GFX9Insts, FeatureDoesNotSupportSRAMECC]
|
|
>;
|
|
|
|
def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
|
|
"volcanic-islands",
|
|
[FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
|
|
FeatureWavefrontSize64, FeatureFlatAddressSpace,
|
|
FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
|
|
FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
|
|
FeatureScalarStores, FeatureInv2PiInlineImm,
|
|
FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
|
|
FeatureIntClamp, FeatureTrigReducedRange, FeatureDoesNotSupportSRAMECC,
|
|
FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts
|
|
]
|
|
>;
|
|
|
|
def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
|
|
"gfx9",
|
|
[FeatureFP64, FeatureLocalMemorySize65536,
|
|
FeatureWavefrontSize64, FeatureFlatAddressSpace,
|
|
FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
|
|
FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
|
|
FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
|
|
FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
|
|
FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
|
|
FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
|
|
FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
|
|
FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16
|
|
]
|
|
>;
|
|
|
|
def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
|
|
"gfx10",
|
|
[FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
|
|
FeatureFlatAddressSpace,
|
|
FeatureCIInsts, Feature16BitInsts,
|
|
FeatureSMemRealTime, FeatureInv2PiInlineImm,
|
|
FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
|
|
FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
|
|
FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
|
|
FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
|
|
FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
|
|
FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking,
|
|
FeatureVOP3Literal, FeatureDPP8, FeatureNoDataDepHazard,
|
|
FeatureDoesNotSupportSRAMECC
|
|
]
|
|
>;
|
|
|
|
class FeatureSet<list<SubtargetFeature> Features_> {
|
|
list<SubtargetFeature> Features = Features_;
|
|
}
|
|
|
|
def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
|
|
FeatureFastFMAF32,
|
|
HalfRate64Ops,
|
|
FeatureLDSBankCount32,
|
|
FeatureDoesNotSupportXNACK,
|
|
FeatureCodeObjectV3]>;
|
|
|
|
def FeatureISAVersion6_0_1 : FeatureSet<
|
|
[FeatureSouthernIslands,
|
|
FeatureLDSBankCount32,
|
|
FeatureDoesNotSupportXNACK,
|
|
FeatureCodeObjectV3]>;
|
|
|
|
def FeatureISAVersion7_0_0 : FeatureSet<
|
|
[FeatureSeaIslands,
|
|
FeatureLDSBankCount32,
|
|
FeatureDoesNotSupportXNACK,
|
|
FeatureCodeObjectV3]>;
|
|
|
|
def FeatureISAVersion7_0_1 : FeatureSet<
|
|
[FeatureSeaIslands,
|
|
HalfRate64Ops,
|
|
FeatureLDSBankCount32,
|
|
FeatureFastFMAF32,
|
|
FeatureDoesNotSupportXNACK,
|
|
FeatureCodeObjectV3]>;
|
|
|
|
def FeatureISAVersion7_0_2 : FeatureSet<
|
|
[FeatureSeaIslands,
|
|
FeatureLDSBankCount16,
|
|
FeatureFastFMAF32,
|
|
FeatureDoesNotSupportXNACK,
|
|
FeatureCodeObjectV3]>;
|
|
|
|
def FeatureISAVersion7_0_3 : FeatureSet<
|
|
[FeatureSeaIslands,
|
|
FeatureLDSBankCount16,
|
|
FeatureDoesNotSupportXNACK,
|
|
FeatureCodeObjectV3]>;
|
|
|
|
def FeatureISAVersion7_0_4 : FeatureSet<
|
|
[FeatureSeaIslands,
|
|
FeatureLDSBankCount32,
|
|
FeatureDoesNotSupportXNACK,
|
|
FeatureCodeObjectV3]>;
|
|
|
|
def FeatureISAVersion8_0_1 : FeatureSet<
|
|
[FeatureVolcanicIslands,
|
|
FeatureFastFMAF32,
|
|
HalfRate64Ops,
|
|
FeatureLDSBankCount32,
|
|
FeatureXNACK,
|
|
FeatureUnpackedD16VMem,
|
|
FeatureCodeObjectV3]>;
|
|
|
|
def FeatureISAVersion8_0_2 : FeatureSet<
|
|
[FeatureVolcanicIslands,
|
|
FeatureLDSBankCount32,
|
|
FeatureSGPRInitBug,
|
|
FeatureUnpackedD16VMem,
|
|
FeatureDoesNotSupportXNACK,
|
|
FeatureCodeObjectV3]>;
|
|
|
|
def FeatureISAVersion8_0_3 : FeatureSet<
|
|
[FeatureVolcanicIslands,
|
|
FeatureLDSBankCount32,
|
|
FeatureUnpackedD16VMem,
|
|
FeatureDoesNotSupportXNACK,
|
|
FeatureCodeObjectV3]>;
|
|
|
|
def FeatureISAVersion8_1_0 : FeatureSet<
|
|
[FeatureVolcanicIslands,
|
|
FeatureLDSBankCount16,
|
|
FeatureXNACK,
|
|
FeatureCodeObjectV3]>;
|
|
|
|
def FeatureISAVersion9_0_0 : FeatureSet<
|
|
[FeatureGFX9,
|
|
FeatureMadMixInsts,
|
|
FeatureLDSBankCount32,
|
|
FeatureCodeObjectV3,
|
|
FeatureDoesNotSupportXNACK,
|
|
FeatureDoesNotSupportSRAMECC]>;
|
|
|
|
def FeatureISAVersion9_0_2 : FeatureSet<
|
|
[FeatureGFX9,
|
|
FeatureMadMixInsts,
|
|
FeatureLDSBankCount32,
|
|
FeatureXNACK,
|
|
FeatureDoesNotSupportSRAMECC,
|
|
FeatureCodeObjectV3]>;
|
|
|
|
def FeatureISAVersion9_0_4 : FeatureSet<
|
|
[FeatureGFX9,
|
|
FeatureLDSBankCount32,
|
|
FeatureFmaMixInsts,
|
|
FeatureDoesNotSupportXNACK,
|
|
FeatureDoesNotSupportSRAMECC,
|
|
FeatureCodeObjectV3]>;
|
|
|
|
def FeatureISAVersion9_0_6 : FeatureSet<
|
|
[FeatureGFX9,
|
|
HalfRate64Ops,
|
|
FeatureFmaMixInsts,
|
|
FeatureLDSBankCount32,
|
|
FeatureDLInsts,
|
|
FeatureDot1Insts,
|
|
FeatureDot2Insts,
|
|
FeatureDoesNotSupportXNACK,
|
|
FeatureCodeObjectV3]>;
|
|
|
|
def FeatureISAVersion9_0_9 : FeatureSet<
|
|
[FeatureGFX9,
|
|
FeatureMadMixInsts,
|
|
FeatureLDSBankCount32,
|
|
FeatureXNACK,
|
|
FeatureCodeObjectV3]>;
|
|
|
|
// TODO: Organize more features into groups.
|
|
def FeatureGroup {
|
|
// Bugs present on gfx10.1.
|
|
list<SubtargetFeature> GFX10_1_Bugs = [
|
|
FeatureVcmpxPermlaneHazard,
|
|
FeatureVMEMtoScalarWriteHazard,
|
|
FeatureSMEMtoVectorWriteHazard,
|
|
FeatureInstFwdPrefetchBug,
|
|
FeatureVcmpxExecWARHazard,
|
|
FeatureLdsBranchVmemWARHazard,
|
|
FeatureNSAtoVMEMBug,
|
|
FeatureFlatSegmentOffsetBug
|
|
];
|
|
}
|
|
|
|
def FeatureISAVersion10_1_0 : FeatureSet<
|
|
!listconcat(FeatureGroup.GFX10_1_Bugs,
|
|
[FeatureGFX10,
|
|
FeatureLDSBankCount32,
|
|
FeatureDLInsts,
|
|
FeatureNSAEncoding,
|
|
FeatureWavefrontSize64,
|
|
FeatureScalarStores,
|
|
FeatureScalarAtomics,
|
|
FeatureScalarFlatScratchInsts,
|
|
FeatureLdsMisalignedBug,
|
|
FeatureDoesNotSupportXNACK,
|
|
FeatureCodeObjectV3])>;
|
|
|
|
def FeatureISAVersion10_1_1 : FeatureSet<
|
|
!listconcat(FeatureGroup.GFX10_1_Bugs,
|
|
[FeatureGFX10,
|
|
FeatureLDSBankCount32,
|
|
FeatureDLInsts,
|
|
FeatureDot1Insts,
|
|
FeatureDot2Insts,
|
|
FeatureDot5Insts,
|
|
FeatureDot6Insts,
|
|
FeatureNSAEncoding,
|
|
FeatureWavefrontSize64,
|
|
FeatureScalarStores,
|
|
FeatureScalarAtomics,
|
|
FeatureScalarFlatScratchInsts,
|
|
FeatureDoesNotSupportXNACK,
|
|
FeatureCodeObjectV3])>;
|
|
|
|
def FeatureISAVersion10_1_2 : FeatureSet<
|
|
!listconcat(FeatureGroup.GFX10_1_Bugs,
|
|
[FeatureGFX10,
|
|
FeatureLDSBankCount32,
|
|
FeatureDLInsts,
|
|
FeatureDot1Insts,
|
|
FeatureDot2Insts,
|
|
FeatureDot5Insts,
|
|
FeatureDot6Insts,
|
|
FeatureNSAEncoding,
|
|
FeatureWavefrontSize64,
|
|
FeatureScalarStores,
|
|
FeatureScalarAtomics,
|
|
FeatureScalarFlatScratchInsts,
|
|
FeatureLdsMisalignedBug,
|
|
FeatureDoesNotSupportXNACK,
|
|
FeatureCodeObjectV3])>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def AMDGPUInstrInfo : InstrInfo {
|
|
let guessInstructionProperties = 1;
|
|
let noNamedPositionallyEncodedOperands = 1;
|
|
}
|
|
|
|
def AMDGPUAsmParser : AsmParser {
|
|
// Some of the R600 registers have the same name, so this crashes.
|
|
// For example T0_XYZW and T0_XY both have the asm name T0.
|
|
let ShouldEmitMatchRegisterName = 0;
|
|
}
|
|
|
|
def AMDGPUAsmWriter : AsmWriter {
|
|
int PassSubtarget = 1;
|
|
}
|
|
|
|
def AMDGPUAsmVariants {
|
|
string Default = "Default";
|
|
int Default_ID = 0;
|
|
string VOP3 = "VOP3";
|
|
int VOP3_ID = 1;
|
|
string SDWA = "SDWA";
|
|
int SDWA_ID = 2;
|
|
string SDWA9 = "SDWA9";
|
|
int SDWA9_ID = 3;
|
|
string DPP = "DPP";
|
|
int DPP_ID = 4;
|
|
string Disable = "Disable";
|
|
int Disable_ID = 5;
|
|
}
|
|
|
|
def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
|
|
let Variant = AMDGPUAsmVariants.Default_ID;
|
|
let Name = AMDGPUAsmVariants.Default;
|
|
}
|
|
|
|
def VOP3AsmParserVariant : AsmParserVariant {
|
|
let Variant = AMDGPUAsmVariants.VOP3_ID;
|
|
let Name = AMDGPUAsmVariants.VOP3;
|
|
}
|
|
|
|
def SDWAAsmParserVariant : AsmParserVariant {
|
|
let Variant = AMDGPUAsmVariants.SDWA_ID;
|
|
let Name = AMDGPUAsmVariants.SDWA;
|
|
}
|
|
|
|
def SDWA9AsmParserVariant : AsmParserVariant {
|
|
let Variant = AMDGPUAsmVariants.SDWA9_ID;
|
|
let Name = AMDGPUAsmVariants.SDWA9;
|
|
}
|
|
|
|
|
|
def DPPAsmParserVariant : AsmParserVariant {
|
|
let Variant = AMDGPUAsmVariants.DPP_ID;
|
|
let Name = AMDGPUAsmVariants.DPP;
|
|
}
|
|
|
|
def AMDGPU : Target {
|
|
// Pull in Instruction Info:
|
|
let InstructionSet = AMDGPUInstrInfo;
|
|
let AssemblyParsers = [AMDGPUAsmParser];
|
|
let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
|
|
VOP3AsmParserVariant,
|
|
SDWAAsmParserVariant,
|
|
SDWA9AsmParserVariant,
|
|
DPPAsmParserVariant];
|
|
let AssemblyWriters = [AMDGPUAsmWriter];
|
|
let AllowRegisterRenaming = 1;
|
|
}
|
|
|
|
// Dummy Instruction itineraries for pseudo instructions
|
|
def ALU_NULL : FuncUnit;
|
|
def NullALU : InstrItinClass;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Predicate helper class
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def isGFX6 :
|
|
Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
|
|
AssemblerPredicate<"FeatureSouthernIslands">;
|
|
|
|
def isGFX6GFX7 :
|
|
Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
|
|
"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
|
|
AssemblerPredicate<"!FeatureGCN3Encoding,!FeatureGFX10Insts">;
|
|
|
|
def isGFX6GFX7GFX10 :
|
|
Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
|
|
"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
|
|
"Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
|
|
AssemblerPredicate<"!FeatureGCN3Encoding">;
|
|
|
|
def isGFX7Only :
|
|
Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
|
|
AssemblerPredicate<"!FeatureGCN3Encoding,FeatureCIInsts,!FeatureGFX10Insts">;
|
|
|
|
def isGFX7GFX10 :
|
|
Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
|
|
"Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
|
|
AssemblerPredicate<"!FeatureGCN3Encoding,FeatureCIInsts">;
|
|
|
|
def isGFX7GFX8GFX9 :
|
|
Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
|
|
"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
|
|
"Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
|
|
AssemblerPredicate<"FeatureGFX7GFX8GFX9Insts">;
|
|
|
|
def isGFX6GFX7GFX8GFX9 :
|
|
Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
|
|
"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
|
|
"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
|
|
"Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
|
|
AssemblerPredicate<"!FeatureGFX10Insts">;
|
|
|
|
def isGFX7Plus :
|
|
Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
|
|
AssemblerPredicate<"FeatureCIInsts">;
|
|
|
|
def isGFX8Plus :
|
|
Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
|
|
AssemblerPredicate<"FeatureGFX8Insts">;
|
|
|
|
def isGFX8Only : Predicate<"Subtarget->getGeneration() =="
|
|
"AMDGPUSubtarget::VOLCANIC_ISLANDS">,
|
|
AssemblerPredicate <"FeatureVolcanicIslands">;
|
|
|
|
def isGFX9Plus :
|
|
Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
|
|
AssemblerPredicate<"FeatureGFX9Insts">;
|
|
|
|
def isGFX9Only : Predicate <
|
|
"Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
|
|
AssemblerPredicate<"FeatureGCN3Encoding,FeatureGFX9Insts">;
|
|
|
|
def isGFX8GFX9 :
|
|
Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
|
|
"Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
|
|
AssemblerPredicate<"FeatureGFX8Insts,FeatureGCN3Encoding">;
|
|
|
|
def isGFX10Plus :
|
|
Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
|
|
AssemblerPredicate<"FeatureGFX10Insts">;
|
|
|
|
def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
|
|
AssemblerPredicate<"FeatureFlatAddressSpace">;
|
|
|
|
def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
|
|
AssemblerPredicate<"FeatureFlatGlobalInsts">;
|
|
def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
|
|
AssemblerPredicate<"FeatureFlatScratchInsts">;
|
|
def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">,
|
|
AssemblerPredicate<"FeatureScalarFlatScratchInsts">;
|
|
def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
|
|
AssemblerPredicate<"FeatureGFX9Insts">;
|
|
|
|
def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
|
|
AssemblerPredicate<"FeatureUnpackedD16VMem">;
|
|
def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
|
|
AssemblerPredicate<"!FeatureUnpackedD16VMem">;
|
|
|
|
def D16PreservesUnusedBits :
|
|
Predicate<"Subtarget->d16PreservesUnusedBits()">,
|
|
AssemblerPredicate<"FeatureGFX9Insts,!FeatureSRAMECC">;
|
|
|
|
def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
|
|
def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
|
|
|
|
def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
|
|
AssemblerPredicate<"FeatureGFX9Insts">;
|
|
|
|
def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
|
|
AssemblerPredicate<"FeatureAddNoCarryInsts">;
|
|
|
|
def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">;
|
|
|
|
def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
|
|
AssemblerPredicate<"Feature16BitInsts">;
|
|
def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
|
|
AssemblerPredicate<"FeatureVOP3P">;
|
|
|
|
def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
|
|
AssemblerPredicate<"FeatureSDWA,FeatureVolcanicIslands">;
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|
|
|
def HasSDWA9 :
|
|
Predicate<"Subtarget->hasSDWA()">,
|
|
AssemblerPredicate<"FeatureGCN3Encoding,FeatureGFX9Insts,FeatureSDWA">;
|
|
|
|
def HasSDWA10 :
|
|
Predicate<"Subtarget->hasSDWA()">,
|
|
AssemblerPredicate<"!FeatureGCN3Encoding,FeatureGFX10Insts,FeatureSDWA">;
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|
|
|
def HasDPP : Predicate<"Subtarget->hasDPP()">,
|
|
AssemblerPredicate<"FeatureGCN3Encoding,FeatureDPP">;
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|
|
|
def HasDPP8 : Predicate<"Subtarget->hasDPP8()">,
|
|
AssemblerPredicate<"!FeatureGCN3Encoding,FeatureGFX10Insts,FeatureDPP8">;
|
|
|
|
def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
|
|
AssemblerPredicate<"FeatureR128A16">;
|
|
|
|
def HasDPP16 : Predicate<"Subtarget->hasDPP()">,
|
|
AssemblerPredicate<"!FeatureGCN3Encoding,FeatureGFX10Insts,FeatureDPP">;
|
|
|
|
def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
|
|
AssemblerPredicate<"FeatureIntClamp">;
|
|
|
|
def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
|
|
AssemblerPredicate<"FeatureMadMixInsts">;
|
|
|
|
def HasScalarStores : Predicate<"Subtarget->hasScalarStores()">,
|
|
AssemblerPredicate<"FeatureScalarStores">;
|
|
|
|
def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
|
|
AssemblerPredicate<"FeatureScalarAtomics">;
|
|
|
|
def HasNoSdstCMPX : Predicate<"Subtarget->hasNoSdstCMPX()">,
|
|
AssemblerPredicate<"FeatureNoSdstCMPX">;
|
|
|
|
def HasSdstCMPX : Predicate<"!Subtarget->hasNoSdstCMPX()">,
|
|
AssemblerPredicate<"!FeatureNoSdstCMPX">;
|
|
|
|
def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
|
|
def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
|
|
def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
|
|
AssemblerPredicate<"FeatureVGPRIndexMode">;
|
|
def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
|
|
AssemblerPredicate<"FeatureMovrel">;
|
|
|
|
def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
|
|
AssemblerPredicate<"FeatureFmaMixInsts">;
|
|
|
|
def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
|
|
AssemblerPredicate<"FeatureDLInsts">;
|
|
|
|
def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">,
|
|
AssemblerPredicate<"FeatureDot1Insts">;
|
|
|
|
def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">,
|
|
AssemblerPredicate<"FeatureDot2Insts">;
|
|
|
|
def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">,
|
|
AssemblerPredicate<"FeatureDot5Insts">;
|
|
|
|
def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">,
|
|
AssemblerPredicate<"FeatureDot6Insts">;
|
|
|
|
def EnableLateCFGStructurize : Predicate<
|
|
"EnableLateStructurizeCFG">;
|
|
|
|
// Include AMDGPU TD files
|
|
include "SISchedule.td"
|
|
include "GCNProcessors.td"
|
|
include "AMDGPUInstrInfo.td"
|
|
include "AMDGPURegisterInfo.td"
|
|
include "AMDGPURegisterBanks.td"
|
|
include "AMDGPUInstructions.td"
|
|
include "SIInstrInfo.td"
|
|
include "AMDGPUCallingConv.td"
|
|
include "AMDGPUSearchableTables.td"
|