llvm-project/llvm/test/tools/llvm-exegesis/X86
Vy Nguyen ee7caa7593 Reland [llvm-exegesis] Add benchmark latency option on X86 that uses LBR for more precise measurements.
Starting with Skylake, the LBR contains the precise number of cycles between the two
        consecutive branches.
        Making use of this will hopefully make the measurements more precise than the
        existing methods of using RDTSC.

                Differential Revision: https://reviews.llvm.org/D77422

New change: check for existence of field `cycles` in perf_branch_entry before enabling this mode.
This should prevent compilation errors when building for older kernel whose headers don't support it.
2020-07-27 12:38:05 -04:00
..
lbr Reland [llvm-exegesis] Add benchmark latency option on X86 that uses LBR for more precise measurements. 2020-07-27 12:38:05 -04:00
analysis-cluster-stabilization-config.test
analysis-cluster-stabilization.test
analysis-clustering-algorithms.test
analysis-epsilons.test
analysis-inconsistencies-uops-backwards.test
analysis-inconsistencies-uops.test
analysis-naive-cluster-stabilization.test
analysis-naive-clusterization.test
analysis-noise.test
analysis-same-cluster-for-ops-in-different-sched-clusters.test
analysis-uops-backwards.test
analysis-uops-variant.test
analysis-uops.test
inverse_throughput-by-opcode-name.s
latency-CMOV32rr.s
latency-LEA64_32r.s [llvm-exegesis] Fix support for LEA64_32r. 2020-01-21 13:58:23 +01:00
latency-LEA64r.s
latency-SBB8rr.s
latency-SETCCr-cond-codes-sweep.s [llvm-exegesis] Exploring X86::OperandType::OPERAND_COND_CODE 2020-02-12 21:33:52 +03:00
latency-SQRTSSr.s [llvm-exegesis] Fix 44b9942898. 2019-12-02 16:13:27 +01:00
latency-by-opcode-name.s
lit.local.cfg
max-configs.test
uops-ADD32mi8.s
uops-ADD32mr.s
uops-ADD32rm.s
uops-ADD_F32m.s
uops-BEXTR32rm.s
uops-BSF16rm.s
uops-BTR64mr.s
uops-CMOV16rm-noreg.s
uops-LEA64r.s
uops-VFMADDSS4rm.s [X86] Model MXCSR for AVX instructions other than AVX512 2019-12-03 08:53:47 +08:00
uops-XCHG64rr.s
uops-by-opcode-name.s