forked from OSchip/llvm-project
066ebbfd46
Summary: This isn't testable for AArch64 by itself so this patch also adds support for constant immediates in the pattern and physical register uses in the result. The new IntOperandMatcher matches the constant in patterns such as '(set $rd:GPR32, (G_XOR $rs:GPR32, -1))'. It's always safe to fold immediates into an instruction so this is the first rule that will match across multiple BB's. The Renderer hierarchy is responsible for adding operands to the result instruction. Renderers can copy operands (CopyRenderer) or add physical registers (in particular %wzr and %xzr) to the result instruction in any order (OperandMatchers now import the operand names from SelectionDAG to allow renderers to access any operand). This allows us to emit the result instruction for: %1 = G_XOR %0, -1 --> %1 = ORNWrr %wzr, %0 %1 = G_XOR -1, %0 --> %1 = ORNWrr %wzr, %0 although the latter is untested since the matcher/importer has not been taught about commutativity yet. Added BuildMIAction which can build new instructions and mutate them where possible. W.r.t the mutation aspect, MatchActions are now told the name of an instruction they can recycle and BuildMIAction will emit mutation code when the renderers are appropriate. They are appropriate when all operands are rendered using CopyRenderer and the indices are the same as the matcher. This currently assumes that all operands have at least one matcher. Finally, this change also fixes a crash in AArch64InstructionSelector::select() caused by an immediate operand passing isImm() rather than isCImm(). This was uncovered by the other changes and was detected by existing tests. Depends on D29711 Reviewers: t.p.northover, ab, qcolombet, rovka, aditya_nandakumar, javed.absar Reviewed By: rovka Subscribers: aemerson, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29712 llvm-svn: 296131 |
||
|---|---|---|
| .. | ||
| 2003-08-03-PassCode.td | ||
| 2006-09-18-LargeInt.td | ||
| 2010-03-24-PrematureDefaults.td | ||
| AnonDefinitionOnDemand.td | ||
| AsmPredicateCondsEmission.td | ||
| AsmVariant.td | ||
| BitOffsetDecoder.td | ||
| BitsInit.td | ||
| BitsInitOverflow.td | ||
| CStyleComment.td | ||
| ClassInstanceValue.td | ||
| Dag.td | ||
| DefmInherit.td | ||
| DefmInsideMultiClass.td | ||
| DuplicateFieldValues.td | ||
| FieldAccess.td | ||
| ForeachList.td | ||
| ForeachLoop.td | ||
| ForwardRef.td | ||
| GeneralList.td | ||
| GlobalISelEmitter.td | ||
| Include.inc | ||
| Include.td | ||
| IntBitInit.td | ||
| LazyChange.td | ||
| LetInsideMultiClasses.td | ||
| ListArgs.td | ||
| ListArgsSimple.td | ||
| ListConversion.td | ||
| ListManip.td | ||
| ListOfList.td | ||
| ListSlices.td | ||
| LoLoL.td | ||
| MultiClass.td | ||
| MultiClassDefName.td | ||
| MultiClassInherit.td | ||
| MultiPat.td | ||
| NestedForeach.td | ||
| Paste.td | ||
| RegisterBankEmitter.td | ||
| SetTheory.td | ||
| SiblingForeach.td | ||
| Slice.td | ||
| String.td | ||
| SuperSubclassSameName.td | ||
| TargetInstrInfo.td | ||
| TargetInstrSpec.td | ||
| TemplateArgRename.td | ||
| Tree.td | ||
| TreeNames.td | ||
| TwoLevelName.td | ||
| UnsetBitInit.td | ||
| UnterminatedComment.td | ||
| ValidIdentifiers.td | ||
| cast-list-initializer.td | ||
| cast.td | ||
| defmclass.td | ||
| eq.td | ||
| eqbit.td | ||
| foreach.td | ||
| if-empty-list-arg.td | ||
| if.td | ||
| ifbit.td | ||
| intrinsic-long-name.td | ||
| intrinsic-varargs.td | ||
| lisp.td | ||
| list-element-bitref.td | ||
| listconcat.td | ||
| lit.local.cfg | ||
| math.td | ||
| nested-comment.td | ||
| pr8330.td | ||
| strconcat.td | ||
| subst.td | ||
| subst2.td | ||
| trydecode-emission.td | ||
| trydecode-emission2.td | ||
| trydecode-emission3.td | ||
| usevalname.td | ||