llvm-project/llvm/test/CodeGen
Tim Northover 232cdb3d30 ARM: allow rewriting frame indexes for all prefetch variants.
For some reason we could handle PLD but not PLDW or PLI, but all of them can
potentially refer to the stack region (if weirdly for PLI).
2019-11-14 14:26:28 +00:00
..
AArch64 [AArch64][SVE] Implement floating-point comparison & reduction intrinsics 2019-11-14 13:47:08 +00:00
AMDGPU [AMDGPU] Fixed dpp test. NFC. 2019-11-13 16:38:54 -08:00
ARC
ARM ARM: allow rewriting frame indexes for all prefetch variants. 2019-11-14 14:26:28 +00:00
AVR
BPF [BPF] generate BTF_KIND_VARs for all non-static globals 2019-11-12 14:34:08 -08:00
Generic [CodeGen] [ExpandReduction] Fix the bug for ExpandReduction() when vector size isn't power of 2 2019-11-02 23:59:12 -04:00
Hexagon [Hexagon] Fix vector spill expansion to use proper alignment 2019-11-12 09:43:21 -06:00
Inputs
Lanai [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
MIR [MIR] Add MIR parsing for heap alloc site instruction markers 2019-11-05 12:57:45 -08:00
MSP430 [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine (4) 2019-11-13 09:23:08 +01:00
Mips [Mips] Add rematerialization support for ldi.fmt 2019-11-13 11:33:52 +01:00
NVPTX [NVPTX] Added llvm.nvvm.mma.m8n8k4.* intrinsics 2019-10-28 13:55:30 -07:00
PowerPC [NFC] Add one test for PowerPC to verify the sext_inreg for vector type. 2019-11-14 10:57:05 +00:00
RISCV Revert "[RISCV] Fix wrong CFI directives" 2019-11-13 13:28:33 +00:00
SPARC
SystemZ [X86] Add more add/sub carry tests 2019-11-12 11:36:59 +02:00
Thumb (Re)generate various tests. NFC 2019-10-08 16:16:26 +00:00
Thumb2 [ARM,MVE] Add intrinsics for contiguous load/stores. 2019-11-13 12:47:00 +00:00
WebAssembly [WebAssembly] Add experimental SIMD dot product instruction 2019-11-01 10:45:48 -07:00
WinCFGuard [WinCFG] Handle constant casts carefully in .gfids emission 2019-11-01 13:32:03 -07:00
WinEH [Windows] Replace TrapUnreachable with an int3 insertion pass 2019-09-09 23:04:25 +00:00
X86 [X86] Don't set the operation action for i16 SINT_TO_FP to Promote just because SSE1 is enabled. 2019-11-13 14:07:56 -08:00
XCore