forked from OSchip/llvm-project
119 lines
4.0 KiB
C++
119 lines
4.0 KiB
C++
//===--- SystemZ.cpp - Implement SystemZ target feature support -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements SystemZ TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZ.h"
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#include "clang/Basic/Builtins.h"
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#include "clang/Basic/LangOptions.h"
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#include "clang/Basic/MacroBuilder.h"
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#include "clang/Basic/TargetBuiltins.h"
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#include "llvm/ADT/StringSwitch.h"
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using namespace clang;
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using namespace clang::targets;
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const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = {
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#define BUILTIN(ID, TYPE, ATTRS) \
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{#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
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#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
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{#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
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#include "clang/Basic/BuiltinsSystemZ.def"
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};
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const char *const SystemZTargetInfo::GCCRegNames[] = {
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
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"r11", "r12", "r13", "r14", "r15", "f0", "f2", "f4", "f6", "f1", "f3",
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"f5", "f7", "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
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};
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ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const {
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return llvm::makeArrayRef(GCCRegNames);
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}
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bool SystemZTargetInfo::validateAsmConstraint(
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const char *&Name, TargetInfo::ConstraintInfo &Info) const {
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switch (*Name) {
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default:
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return false;
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case 'a': // Address register
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case 'd': // Data register (equivalent to 'r')
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case 'f': // Floating-point register
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Info.setAllowsRegister();
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return true;
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case 'I': // Unsigned 8-bit constant
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case 'J': // Unsigned 12-bit constant
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case 'K': // Signed 16-bit constant
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case 'L': // Signed 20-bit displacement (on all targets we support)
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case 'M': // 0x7fffffff
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return true;
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case 'Q': // Memory with base and unsigned 12-bit displacement
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case 'R': // Likewise, plus an index
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case 'S': // Memory with base and signed 20-bit displacement
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case 'T': // Likewise, plus an index
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Info.setAllowsMemory();
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return true;
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}
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}
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int SystemZTargetInfo::getISARevision(const StringRef &Name) const {
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return llvm::StringSwitch<int>(Name)
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.Cases("arch8", "z10", 8)
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.Cases("arch9", "z196", 9)
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.Cases("arch10", "zEC12", 10)
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.Cases("arch11", "z13", 11)
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.Cases("arch12", "z14", 12)
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.Default(-1);
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}
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bool SystemZTargetInfo::hasFeature(StringRef Feature) const {
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return llvm::StringSwitch<bool>(Feature)
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.Case("systemz", true)
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.Case("arch8", ISARevision >= 8)
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.Case("arch9", ISARevision >= 9)
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.Case("arch10", ISARevision >= 10)
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.Case("arch11", ISARevision >= 11)
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.Case("arch12", ISARevision >= 12)
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.Case("htm", HasTransactionalExecution)
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.Case("vx", HasVector)
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.Default(false);
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}
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void SystemZTargetInfo::getTargetDefines(const LangOptions &Opts,
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MacroBuilder &Builder) const {
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Builder.defineMacro("__s390__");
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Builder.defineMacro("__s390x__");
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Builder.defineMacro("__zarch__");
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Builder.defineMacro("__LONG_DOUBLE_128__");
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Builder.defineMacro("__ARCH__", Twine(ISARevision));
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
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if (HasTransactionalExecution)
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Builder.defineMacro("__HTM__");
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if (HasVector)
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Builder.defineMacro("__VX__");
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if (Opts.ZVector)
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Builder.defineMacro("__VEC__", "10302");
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}
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ArrayRef<Builtin::Info> SystemZTargetInfo::getTargetBuiltins() const {
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return llvm::makeArrayRef(BuiltinInfo, clang::SystemZ::LastTSBuiltin -
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Builtin::FirstTSBuiltin);
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}
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