forked from OSchip/llvm-project
496 lines
17 KiB
C++
496 lines
17 KiB
C++
//===-- PPCTargetTransformInfo.cpp - PPC specific TTI ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "PPCTargetTransformInfo.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/CodeGen/CostTable.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "ppctti"
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static cl::opt<bool> DisablePPCConstHoist("disable-ppc-constant-hoisting",
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cl::desc("disable constant hoisting on PPC"), cl::init(false), cl::Hidden);
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// This is currently only used for the data prefetch pass which is only enabled
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// for BG/Q by default.
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static cl::opt<unsigned>
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CacheLineSize("ppc-loop-prefetch-cache-line", cl::Hidden, cl::init(64),
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cl::desc("The loop prefetch cache line size"));
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static cl::opt<bool>
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EnablePPCColdCC("ppc-enable-coldcc", cl::Hidden, cl::init(false),
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cl::desc("Enable using coldcc calling conv for cold "
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"internal functions"));
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//===----------------------------------------------------------------------===//
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//
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// PPC cost model.
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//
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//===----------------------------------------------------------------------===//
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TargetTransformInfo::PopcntSupportKind
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PPCTTIImpl::getPopcntSupport(unsigned TyWidth) {
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assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
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if (ST->hasPOPCNTD() != PPCSubtarget::POPCNTD_Unavailable && TyWidth <= 64)
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return ST->hasPOPCNTD() == PPCSubtarget::POPCNTD_Slow ?
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TTI::PSK_SlowHardware : TTI::PSK_FastHardware;
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return TTI::PSK_Software;
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}
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int PPCTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
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if (DisablePPCConstHoist)
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return BaseT::getIntImmCost(Imm, Ty);
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assert(Ty->isIntegerTy());
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unsigned BitSize = Ty->getPrimitiveSizeInBits();
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if (BitSize == 0)
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return ~0U;
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if (Imm == 0)
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return TTI::TCC_Free;
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if (Imm.getBitWidth() <= 64) {
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if (isInt<16>(Imm.getSExtValue()))
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return TTI::TCC_Basic;
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if (isInt<32>(Imm.getSExtValue())) {
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// A constant that can be materialized using lis.
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if ((Imm.getZExtValue() & 0xFFFF) == 0)
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return TTI::TCC_Basic;
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return 2 * TTI::TCC_Basic;
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}
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}
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return 4 * TTI::TCC_Basic;
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}
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int PPCTTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
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Type *Ty) {
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if (DisablePPCConstHoist)
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return BaseT::getIntImmCost(IID, Idx, Imm, Ty);
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assert(Ty->isIntegerTy());
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unsigned BitSize = Ty->getPrimitiveSizeInBits();
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if (BitSize == 0)
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return ~0U;
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switch (IID) {
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default:
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return TTI::TCC_Free;
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case Intrinsic::sadd_with_overflow:
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case Intrinsic::uadd_with_overflow:
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case Intrinsic::ssub_with_overflow:
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case Intrinsic::usub_with_overflow:
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if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<16>(Imm.getSExtValue()))
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return TTI::TCC_Free;
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break;
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case Intrinsic::experimental_stackmap:
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if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
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return TTI::TCC_Free;
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break;
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case Intrinsic::experimental_patchpoint_void:
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case Intrinsic::experimental_patchpoint_i64:
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if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
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return TTI::TCC_Free;
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break;
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}
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return PPCTTIImpl::getIntImmCost(Imm, Ty);
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}
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int PPCTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
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Type *Ty) {
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if (DisablePPCConstHoist)
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return BaseT::getIntImmCost(Opcode, Idx, Imm, Ty);
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assert(Ty->isIntegerTy());
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unsigned BitSize = Ty->getPrimitiveSizeInBits();
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if (BitSize == 0)
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return ~0U;
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unsigned ImmIdx = ~0U;
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bool ShiftedFree = false, RunFree = false, UnsignedFree = false,
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ZeroFree = false;
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switch (Opcode) {
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default:
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return TTI::TCC_Free;
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case Instruction::GetElementPtr:
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// Always hoist the base address of a GetElementPtr. This prevents the
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// creation of new constants for every base constant that gets constant
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// folded with the offset.
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if (Idx == 0)
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return 2 * TTI::TCC_Basic;
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return TTI::TCC_Free;
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case Instruction::And:
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RunFree = true; // (for the rotate-and-mask instructions)
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LLVM_FALLTHROUGH;
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case Instruction::Add:
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case Instruction::Or:
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case Instruction::Xor:
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ShiftedFree = true;
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LLVM_FALLTHROUGH;
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case Instruction::Sub:
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case Instruction::Mul:
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case Instruction::Shl:
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case Instruction::LShr:
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case Instruction::AShr:
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ImmIdx = 1;
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break;
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case Instruction::ICmp:
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UnsignedFree = true;
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ImmIdx = 1;
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// Zero comparisons can use record-form instructions.
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LLVM_FALLTHROUGH;
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case Instruction::Select:
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ZeroFree = true;
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break;
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case Instruction::PHI:
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case Instruction::Call:
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case Instruction::Ret:
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case Instruction::Load:
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case Instruction::Store:
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break;
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}
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if (ZeroFree && Imm == 0)
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return TTI::TCC_Free;
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if (Idx == ImmIdx && Imm.getBitWidth() <= 64) {
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if (isInt<16>(Imm.getSExtValue()))
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return TTI::TCC_Free;
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if (RunFree) {
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if (Imm.getBitWidth() <= 32 &&
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(isShiftedMask_32(Imm.getZExtValue()) ||
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isShiftedMask_32(~Imm.getZExtValue())))
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return TTI::TCC_Free;
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if (ST->isPPC64() &&
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(isShiftedMask_64(Imm.getZExtValue()) ||
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isShiftedMask_64(~Imm.getZExtValue())))
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return TTI::TCC_Free;
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}
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if (UnsignedFree && isUInt<16>(Imm.getZExtValue()))
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return TTI::TCC_Free;
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if (ShiftedFree && (Imm.getZExtValue() & 0xFFFF) == 0)
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return TTI::TCC_Free;
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}
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return PPCTTIImpl::getIntImmCost(Imm, Ty);
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}
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unsigned PPCTTIImpl::getUserCost(const User *U,
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ArrayRef<const Value *> Operands) {
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if (U->getType()->isVectorTy()) {
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// Instructions that need to be split should cost more.
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std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, U->getType());
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return LT.first * BaseT::getUserCost(U, Operands);
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}
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return BaseT::getUserCost(U, Operands);
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}
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void PPCTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::UnrollingPreferences &UP) {
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if (ST->getDarwinDirective() == PPC::DIR_A2) {
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// The A2 is in-order with a deep pipeline, and concatenation unrolling
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// helps expose latency-hiding opportunities to the instruction scheduler.
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UP.Partial = UP.Runtime = true;
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// We unroll a lot on the A2 (hundreds of instructions), and the benefits
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// often outweigh the cost of a division to compute the trip count.
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UP.AllowExpensiveTripCount = true;
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}
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BaseT::getUnrollingPreferences(L, SE, UP);
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}
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// This function returns true to allow using coldcc calling convention.
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// Returning true results in coldcc being used for functions which are cold at
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// all call sites when the callers of the functions are not calling any other
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// non coldcc functions.
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bool PPCTTIImpl::useColdCCForColdCall(Function &F) {
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return EnablePPCColdCC;
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}
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bool PPCTTIImpl::enableAggressiveInterleaving(bool LoopHasReductions) {
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// On the A2, always unroll aggressively. For QPX unaligned loads, we depend
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// on combining the loads generated for consecutive accesses, and failure to
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// do so is particularly expensive. This makes it much more likely (compared
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// to only using concatenation unrolling).
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if (ST->getDarwinDirective() == PPC::DIR_A2)
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return true;
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return LoopHasReductions;
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}
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const PPCTTIImpl::TTI::MemCmpExpansionOptions *
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PPCTTIImpl::enableMemCmpExpansion(bool IsZeroCmp) const {
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static const auto Options = []() {
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TTI::MemCmpExpansionOptions Options;
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Options.LoadSizes.push_back(8);
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Options.LoadSizes.push_back(4);
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Options.LoadSizes.push_back(2);
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Options.LoadSizes.push_back(1);
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return Options;
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}();
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return &Options;
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}
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bool PPCTTIImpl::enableInterleavedAccessVectorization() {
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return true;
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}
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unsigned PPCTTIImpl::getNumberOfRegisters(bool Vector) {
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if (Vector && !ST->hasAltivec() && !ST->hasQPX())
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return 0;
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return ST->hasVSX() ? 64 : 32;
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}
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unsigned PPCTTIImpl::getRegisterBitWidth(bool Vector) const {
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if (Vector) {
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if (ST->hasQPX()) return 256;
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if (ST->hasAltivec()) return 128;
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return 0;
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}
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if (ST->isPPC64())
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return 64;
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return 32;
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}
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unsigned PPCTTIImpl::getCacheLineSize() {
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// Check first if the user specified a custom line size.
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if (CacheLineSize.getNumOccurrences() > 0)
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return CacheLineSize;
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// On P7, P8 or P9 we have a cache line size of 128.
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unsigned Directive = ST->getDarwinDirective();
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if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
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Directive == PPC::DIR_PWR9)
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return 128;
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// On other processors return a default of 64 bytes.
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return 64;
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}
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unsigned PPCTTIImpl::getPrefetchDistance() {
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// This seems like a reasonable default for the BG/Q (this pass is enabled, by
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// default, only on the BG/Q).
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return 300;
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}
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unsigned PPCTTIImpl::getMaxInterleaveFactor(unsigned VF) {
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unsigned Directive = ST->getDarwinDirective();
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// The 440 has no SIMD support, but floating-point instructions
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// have a 5-cycle latency, so unroll by 5x for latency hiding.
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if (Directive == PPC::DIR_440)
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return 5;
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// The A2 has no SIMD support, but floating-point instructions
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// have a 6-cycle latency, so unroll by 6x for latency hiding.
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if (Directive == PPC::DIR_A2)
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return 6;
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// FIXME: For lack of any better information, do no harm...
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if (Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500)
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return 1;
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// For P7 and P8, floating-point instructions have a 6-cycle latency and
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// there are two execution units, so unroll by 12x for latency hiding.
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// FIXME: the same for P9 as previous gen until POWER9 scheduling is ready
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if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
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Directive == PPC::DIR_PWR9)
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return 12;
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// For most things, modern systems have two execution units (and
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// out-of-order execution).
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return 2;
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}
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int PPCTTIImpl::getArithmeticInstrCost(
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unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info,
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TTI::OperandValueKind Op2Info, TTI::OperandValueProperties Opd1PropInfo,
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TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args) {
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assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");
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// Fallback to the default implementation.
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return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info,
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Opd1PropInfo, Opd2PropInfo);
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}
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int PPCTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
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Type *SubTp) {
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// Legalize the type.
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std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
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// PPC, for both Altivec/VSX and QPX, support cheap arbitrary permutations
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// (at least in the sense that there need only be one non-loop-invariant
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// instruction). We need one such shuffle instruction for each actual
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// register (this is not true for arbitrary shuffles, but is true for the
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// structured types of shuffles covered by TTI::ShuffleKind).
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return LT.first;
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}
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int PPCTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
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const Instruction *I) {
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assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");
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return BaseT::getCastInstrCost(Opcode, Dst, Src);
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}
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int PPCTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
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const Instruction *I) {
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return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
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}
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int PPCTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) {
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assert(Val->isVectorTy() && "This must be a vector type");
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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assert(ISD && "Invalid opcode");
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if (ST->hasVSX() && Val->getScalarType()->isDoubleTy()) {
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// Double-precision scalars are already located in index #0.
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if (Index == 0)
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return 0;
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return BaseT::getVectorInstrCost(Opcode, Val, Index);
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} else if (ST->hasQPX() && Val->getScalarType()->isFloatingPointTy()) {
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// Floating point scalars are already located in index #0.
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if (Index == 0)
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return 0;
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return BaseT::getVectorInstrCost(Opcode, Val, Index);
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}
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// Estimated cost of a load-hit-store delay. This was obtained
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// experimentally as a minimum needed to prevent unprofitable
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// vectorization for the paq8p benchmark. It may need to be
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// raised further if other unprofitable cases remain.
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unsigned LHSPenalty = 2;
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if (ISD == ISD::INSERT_VECTOR_ELT)
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LHSPenalty += 7;
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// Vector element insert/extract with Altivec is very expensive,
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// because they require store and reload with the attendant
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// processor stall for load-hit-store. Until VSX is available,
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// these need to be estimated as very costly.
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if (ISD == ISD::EXTRACT_VECTOR_ELT ||
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ISD == ISD::INSERT_VECTOR_ELT)
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return LHSPenalty + BaseT::getVectorInstrCost(Opcode, Val, Index);
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return BaseT::getVectorInstrCost(Opcode, Val, Index);
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}
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int PPCTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
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unsigned AddressSpace, const Instruction *I) {
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// Legalize the type.
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std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src);
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assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
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"Invalid Opcode");
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int Cost = BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
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bool IsAltivecType = ST->hasAltivec() &&
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(LT.second == MVT::v16i8 || LT.second == MVT::v8i16 ||
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LT.second == MVT::v4i32 || LT.second == MVT::v4f32);
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bool IsVSXType = ST->hasVSX() &&
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(LT.second == MVT::v2f64 || LT.second == MVT::v2i64);
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bool IsQPXType = ST->hasQPX() &&
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(LT.second == MVT::v4f64 || LT.second == MVT::v4f32);
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// VSX has 32b/64b load instructions. Legalization can handle loading of
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// 32b/64b to VSR correctly and cheaply. But BaseT::getMemoryOpCost and
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// PPCTargetLowering can't compute the cost appropriately. So here we
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// explicitly check this case.
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unsigned MemBytes = Src->getPrimitiveSizeInBits();
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if (Opcode == Instruction::Load && ST->hasVSX() && IsAltivecType &&
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(MemBytes == 64 || (ST->hasP8Vector() && MemBytes == 32)))
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return 1;
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// Aligned loads and stores are easy.
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unsigned SrcBytes = LT.second.getStoreSize();
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if (!SrcBytes || !Alignment || Alignment >= SrcBytes)
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return Cost;
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// If we can use the permutation-based load sequence, then this is also
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// relatively cheap (not counting loop-invariant instructions): one load plus
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// one permute (the last load in a series has extra cost, but we're
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// neglecting that here). Note that on the P7, we could do unaligned loads
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// for Altivec types using the VSX instructions, but that's more expensive
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// than using the permutation-based load sequence. On the P8, that's no
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// longer true.
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if (Opcode == Instruction::Load &&
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((!ST->hasP8Vector() && IsAltivecType) || IsQPXType) &&
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Alignment >= LT.second.getScalarType().getStoreSize())
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return Cost + LT.first; // Add the cost of the permutations.
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// For VSX, we can do unaligned loads and stores on Altivec/VSX types. On the
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// P7, unaligned vector loads are more expensive than the permutation-based
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// load sequence, so that might be used instead, but regardless, the net cost
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// is about the same (not counting loop-invariant instructions).
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if (IsVSXType || (ST->hasVSX() && IsAltivecType))
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return Cost;
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// Newer PPC supports unaligned memory access.
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if (TLI->allowsMisalignedMemoryAccesses(LT.second, 0))
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return Cost;
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// PPC in general does not support unaligned loads and stores. They'll need
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// to be decomposed based on the alignment factor.
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// Add the cost of each scalar load or store.
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Cost += LT.first*(SrcBytes/Alignment-1);
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// For a vector type, there is also scalarization overhead (only for
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// stores, loads are expanded using the vector-load + permutation sequence,
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// which is much less expensive).
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if (Src->isVectorTy() && Opcode == Instruction::Store)
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for (int i = 0, e = Src->getVectorNumElements(); i < e; ++i)
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Cost += getVectorInstrCost(Instruction::ExtractElement, Src, i);
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return Cost;
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}
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int PPCTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
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unsigned Factor,
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ArrayRef<unsigned> Indices,
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unsigned Alignment,
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unsigned AddressSpace) {
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assert(isa<VectorType>(VecTy) &&
|
|
"Expect a vector type for interleaved memory op");
|
|
|
|
// Legalize the type.
|
|
std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, VecTy);
|
|
|
|
// Firstly, the cost of load/store operation.
|
|
int Cost = getMemoryOpCost(Opcode, VecTy, Alignment, AddressSpace);
|
|
|
|
// PPC, for both Altivec/VSX and QPX, support cheap arbitrary permutations
|
|
// (at least in the sense that there need only be one non-loop-invariant
|
|
// instruction). For each result vector, we need one shuffle per incoming
|
|
// vector (except that the first shuffle can take two incoming vectors
|
|
// because it does not need to take itself).
|
|
Cost += Factor*(LT.first-1);
|
|
|
|
return Cost;
|
|
}
|
|
|