forked from OSchip/llvm-project
22e7da9597
According to Power ISA V3.0 document, the first source operand of mtvsrdd is constant 0 if r0 is specified. So the corresponding register constraint should be g8rc_nox0. This bug caused wrong output generated by 401.bzip2 when -mcpu=power9 and fdo are specified. Differential Revision: https://reviews.llvm.org/D32880 llvm-svn: 302834 |
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CMakeLists.txt | ||
LLVMBuild.txt | ||
PPCDisassembler.cpp |