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Tim Renouf 35484c9d50 [AMDGPU] New tbuffer intrinsics 
Summary:
This commit adds new intrinsics
  llvm.amdgcn.raw.tbuffer.load
  llvm.amdgcn.struct.tbuffer.load
  llvm.amdgcn.raw.tbuffer.store
  llvm.amdgcn.struct.tbuffer.store

with the following changes from the llvm.amdgcn.tbuffer.* intrinsics:

* there are separate raw and struct versions: raw does not have an index
  arg and sets idxen=0 in the instruction, and struct always sets
  idxen=1 in the instruction even if the index is 0, to allow for the
  fact that gfx9 does bounds checking differently depending on whether
  idxen is set;

* there is a combined format arg (dfmt+nfmt)

* there is a combined cachepolicy arg (glc+slc)

* there are now only two offset args: one for the offset that is
  included in bounds checking and swizzling, to be split between the
  instruction's voffset and immoffset fields, and one for the offset
  that is excluded from bounds checking and swizzling, to go into the
  instruction's soffset field.

The AMDISD::TBUFFER_* SD nodes always have an index operand, all three
offset operands, combined format operand, combined cachepolicy operand,
and an extra idxen operand.

The tbuffer pseudo- and real instructions now also have a combined
format operand.

The obsolescent llvm.amdgcn.tbuffer.* and llvm.SI.tbuffer.store
intrinsics continue to work.

V2: Separate raw and struct intrinsics.
V3: Moved extract_glc and extract_slc defs to a more sensible place.
V4: Rebased on D49995.
V5: Only two separate offset args instead of three.
V6: Pseudo- and real instructions have joint format operand.
V7: Restored optionality of dfmt and nfmt in assembler.
V8: Addressed minor review comments.

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D49026

Change-Id: If22ad77e349fac3a5d2f72dda53c010377d470d4
llvm-svn: 340268
 		2018-08-21 11:06:05 +00:00
..
AsmParser [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
Disassembler AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
InstPrinter [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
MCTargetDesc [AMDGPU] Fix layering issue with AMDGPUHSAMetadataStreamer (NFC) 2018-07-10 20:07:22 +00:00
TargetInfo Remove \brief commands from doxygen comments. 2018-05-01 15:54:18 +00:00
Utils [AMDGPU] Optimize _L image intrinsic to _LZ when lod is zero 2018-08-01 12:12:01 +00:00
AMDGPU.h Revert "AMDGPU: bump AS.MAX_COMMON_ADDRESS to 6 since 32-bit addr space" 2018-08-20 19:31:03 +00:00
AMDGPU.td AMDGPU: Add feature vi-insts 2018-08-07 07:28:46 +00:00
AMDGPUAliasAnalysis.cpp Revert "AMDGPU: bump AS.MAX_COMMON_ADDRESS to 6 since 32-bit addr space" 2018-08-20 19:31:03 +00:00
AMDGPUAliasAnalysis.h
…
AMDGPUAlwaysInlinePass.cpp Reapply "AMDGPU: Force inlining if LDS global address is used" 2018-07-10 14:03:41 +00:00
AMDGPUAnnotateKernelFeatures.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
AMDGPUAnnotateUniformValues.cpp
…
AMDGPUArgumentUsageInfo.cpp AMDGPU/AMDHSA: Remove GridWorkGroupCountX/Y/Z 2018-06-21 18:36:04 +00:00
AMDGPUArgumentUsageInfo.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
AMDGPUAsmPrinter.cpp Reapply "AMDGPU: Fix handling of alignment padding in DAG argument lowering" 2018-07-20 09:05:08 +00:00
AMDGPUAsmPrinter.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
AMDGPUCallLowering.cpp [GlobalISel] Rewrite CallLowering::lowerReturn to accept multiple VRegs per Value 2018-08-02 08:33:31 +00:00
AMDGPUCallLowering.h [GlobalISel] Rewrite CallLowering::lowerReturn to accept multiple VRegs per Value 2018-08-02 08:33:31 +00:00
AMDGPUCallingConv.td AMDGPU: Partially fix handling of packed amdgpu_ps arguments 2018-08-01 19:57:34 +00:00
AMDGPUCodeGenPrepare.cpp [AMDGPU] Use AssumptionCacheTracker in the divrem32 expansion 2018-07-25 17:02:11 +00:00
AMDGPUFeatures.td AMDGPU: Allow fp32-denormals feature for r600 targets 2018-08-01 15:04:36 +00:00
AMDGPUFrameLowering.cpp
…
AMDGPUFrameLowering.h Remove \brief commands from doxygen comments. 2018-05-01 15:54:18 +00:00
AMDGPUGISel.td AMDGPU/GlobalISel: Implement select() for 32-bit @llvm.minnun and @llvm.maxnum 2018-07-13 22:16:03 +00:00
AMDGPUGenRegisterBankInfo.def AMDGPU/GlobalISel: Fix crash in regbankselect on non-power-of-2 types 2018-07-27 06:04:40 +00:00
AMDGPUHSAMetadataStreamer.cpp Reapply "AMDGPU: Fix handling of alignment padding in DAG argument lowering" 2018-07-20 09:05:08 +00:00
AMDGPUHSAMetadataStreamer.h Fix -Wmismatched-tags warning 2018-07-10 22:09:33 +00:00
AMDGPUISelDAGToDAG.cpp [SDAG] Remove the reliance on MI's allocation strategy for 2018-08-14 23:30:32 +00:00
AMDGPUISelLowering.cpp AMDGPU: Custom lower fexp 2018-08-16 17:07:52 +00:00
AMDGPUISelLowering.h AMDGPU: Custom lower fexp 2018-08-16 17:07:52 +00:00
AMDGPUInline.cpp Enrich inline messages 2018-08-05 14:53:08 +00:00
AMDGPUInstrInfo.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
AMDGPUInstrInfo.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
AMDGPUInstrInfo.td AMDGPU: Add clamp bit to dot intrinsics 2018-08-01 01:31:30 +00:00
AMDGPUInstructionSelector.cpp AMDGPU/GlobalISel: Implement select() for 32-bit @llvm.minnun and @llvm.maxnum 2018-07-13 22:16:03 +00:00
AMDGPUInstructionSelector.h AMDGPU/GlobalISel: Implement select() for @llvm.amdgcn.exp 2018-07-13 21:05:14 +00:00
AMDGPUInstructions.td AMDGPU: Reduce code size with fcanonicalize (fneg x) 2018-07-30 12:16:58 +00:00
AMDGPUIntrinsicInfo.cpp [AMDGPU] Update includes for intrinsic changes :( 2018-06-23 03:05:39 +00:00
AMDGPUIntrinsicInfo.h [AMDGPU] Update includes for intrinsic changes :( 2018-06-23 03:05:39 +00:00
AMDGPUIntrinsics.td AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
AMDGPULegalizerInfo.cpp AMDGPU/GlobalISel: Legalize G_INSERT 2018-07-24 02:19:20 +00:00
AMDGPULegalizerInfo.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
AMDGPULibCalls.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AMDGPULibFunc.cpp [AMDGPU] Remove hardcoded address space value from AMDGPULibFunc 2017-11-04 17:37:43 +00:00
AMDGPULibFunc.h AMDGPU: Fix missing C++ mode comment 2018-06-20 19:45:40 +00:00
AMDGPULowerIntrinsics.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
AMDGPULowerKernelArguments.cpp AMDGPU: Stop trying to extend arguments for clover 2018-07-28 12:34:25 +00:00
AMDGPULowerKernelAttributes.cpp AMDGPU: Add pass to optimize reqd_work_group_size 2018-05-18 21:35:00 +00:00
AMDGPUMCInstLower.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
AMDGPUMachineCFGStructurizer.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
AMDGPUMachineFunction.cpp Reapply "AMDGPU: Fix handling of alignment padding in DAG argument lowering" 2018-07-20 09:05:08 +00:00
AMDGPUMachineFunction.h Reapply "AMDGPU: Fix handling of alignment padding in DAG argument lowering" 2018-07-20 09:05:08 +00:00
AMDGPUMachineModuleInfo.cpp Remove \brief commands from doxygen comments. 2018-05-01 15:54:18 +00:00
AMDGPUMachineModuleInfo.h Remove \brief commands from doxygen comments. 2018-05-01 15:54:18 +00:00
AMDGPUMacroFusion.cpp AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers 2018-05-22 02:03:23 +00:00
AMDGPUMacroFusion.h
…
AMDGPUOpenCLEnqueuedBlockLowering.cpp [AMDGPU] Change enqueue kernel handle type 2018-06-13 17:31:51 +00:00
AMDGPUPTNote.h AMDGPU/NFC: Move AMDGPU specific note types to ELF.h 2017-10-12 18:59:54 +00:00
AMDGPUPerfHintAnalysis.cpp [AMDGPU] Do not consider indirect acces through phi for wave limiter 2018-06-11 16:50:49 +00:00
AMDGPUPerfHintAnalysis.h Fix -Winconsistent-missing-overrides in AMDGPU code 2018-05-25 17:46:24 +00:00
AMDGPUPromoteAlloca.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
AMDGPURegAsmNames.inc.cpp
…
AMDGPURegisterBankInfo.cpp AMDGPU/GlobalISel: Define instruction mapping for G_INSERT 2018-08-11 00:51:54 +00:00
AMDGPURegisterBankInfo.h AMDGPU/GlobalISel: Define instruction mapping for G_OR 2018-03-01 21:25:25 +00:00
AMDGPURegisterBanks.td AMDGPU/GlobalISel: Define InstrMappings for G_ICMP 2018-03-01 19:27:10 +00:00
AMDGPURegisterInfo.cpp AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers 2018-05-22 02:03:23 +00:00
AMDGPURegisterInfo.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
AMDGPURegisterInfo.td AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
AMDGPURewriteOutArguments.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AMDGPUSearchableTables.td AMDGPU: Remove old-style image intrinsics 2018-06-21 13:37:45 +00:00
AMDGPUSubtarget.cpp AMDGPU: Address todo for handling 1/(2 pi) 2018-08-15 21:03:55 +00:00
AMDGPUSubtarget.h AMDGPU: Address todo for handling 1/(2 pi) 2018-08-15 21:03:55 +00:00
AMDGPUTargetMachine.cpp run post-RA hazard recognizer pass late 2018-07-16 10:02:41 +00:00
AMDGPUTargetMachine.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
AMDGPUTargetObjectFile.cpp AMDGPU: Fix set but not used warnings related to AMDGPUAS 2017-11-01 19:12:38 +00:00
AMDGPUTargetObjectFile.h Remove \brief commands from doxygen comments. 2018-05-01 15:54:18 +00:00
AMDGPUTargetTransformInfo.cpp AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
AMDGPUTargetTransformInfo.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
AMDGPUUnifyDivergentExitNodes.cpp Move Analysis/Utils/Local.h back to Transforms 2018-06-04 21:23:21 +00:00
AMDGPUUnifyMetadata.cpp Remove \brief commands from doxygen comments. 2018-05-01 15:54:18 +00:00
AMDILCFGStructurizer.cpp AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
AMDKernelCodeT.h Remove @brief commands from doxygen comments, too. 2018-05-01 16:10:38 +00:00
BUFInstructions.td [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
CMakeLists.txt [AMDGPU] Fix layering issue with AMDGPUHSAMetadataStreamer (NFC) 2018-07-10 20:07:22 +00:00
CaymanInstructions.td [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
DSInstructions.td AMDGPU: Add patterns for i32/i64 local atomic load/store 2018-06-22 08:39:52 +00:00
EvergreenInstructions.td AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
FLATInstructions.td AMDGPU: Make various NamedOperands upper case 2018-06-04 14:45:20 +00:00
GCNHazardRecognizer.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
GCNHazardRecognizer.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
GCNILPSched.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
GCNIterativeScheduler.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
GCNIterativeScheduler.h AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental) 2017-11-20 14:35:53 +00:00
GCNMinRegStrategy.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
GCNProcessors.td AMDGPU: Add Vega12 and Vega20 2018-04-30 19:08:16 +00:00
GCNRegPressure.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
GCNRegPressure.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
GCNSchedStrategy.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
GCNSchedStrategy.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
LLVMBuild.txt
…
MIMGInstructions.td [AMDGPU] Optimize _L image intrinsic to _LZ when lod is zero 2018-08-01 12:12:01 +00:00
R600.td Reapply "AMDGPU: Fix handling of alignment padding in DAG argument lowering" 2018-07-20 09:05:08 +00:00
R600AsmPrinter.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
R600AsmPrinter.h AMDGPU: Split R600 AsmPrinter code into its own class 2018-05-24 20:02:01 +00:00
R600ClauseMergePass.cpp AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
R600ControlFlowFinalizer.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
R600Defines.h Remove \brief commands from doxygen comments. 2018-05-01 15:54:18 +00:00
R600EmitClauseMarkers.cpp AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
R600ExpandSpecialInstrs.cpp AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
R600FrameLowering.cpp
…
R600FrameLowering.h
…
R600ISelLowering.cpp AMDGPU/R600: Convert kernel param loads to use PARAM_I_ADDRESS 2018-08-01 18:36:07 +00:00
R600ISelLowering.h AMDGPU/R600: Convert kernel param loads to use PARAM_I_ADDRESS 2018-08-01 18:36:07 +00:00
R600InstrFormats.td AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
R600InstrInfo.cpp [PSV] Update API to be able to use TargetCustom without UB. 2018-08-20 19:23:45 +00:00
R600InstrInfo.h [PSV] Update API to be able to use TargetCustom without UB. 2018-08-20 19:23:45 +00:00
R600Instructions.td AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
R600MachineFunctionInfo.cpp
…
R600MachineFunctionInfo.h
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R600MachineScheduler.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
R600MachineScheduler.h Remove \brief commands from doxygen comments. 2018-05-01 15:54:18 +00:00
R600OpenCLImageTypeLoweringPass.cpp AMDGPU: Rename OpenCL lowering pass to be R600 specific. 2018-05-13 10:04:48 +00:00
R600OptimizeVectorRegisters.cpp AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
R600Packetizer.cpp AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
R600Processors.td AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
R600RegisterInfo.cpp AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
R600RegisterInfo.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
R600RegisterInfo.td AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
R600Schedule.td
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R700Instructions.td AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SIAnnotateControlFlow.cpp Move Analysis/Utils/Local.h back to Transforms 2018-06-04 21:23:21 +00:00
SIDebuggerInsertNops.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SIDefines.h AMDGPU: Turn D16 for MIMG instructions into a regular operand 2018-06-21 13:36:01 +00:00
SIFixSGPRCopies.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SIFixVGPRCopies.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SIFixWWMLiveness.cpp [AMDGPU] Reworked SIFixWWMLiveness 2018-08-02 23:31:32 +00:00
SIFoldOperands.cpp AMDGPU: Check NSZ MI flag when folding omod 2018-08-12 08:44:25 +00:00
SIFormMemoryClauses.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SIFrameLowering.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SIFrameLowering.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SIISelLowering.cpp [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
SIISelLowering.h [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
SIInsertSkips.cpp AMDGPU: Force skip over s_sendmsg and exp instructions 2018-07-30 09:23:59 +00:00
SIInsertWaitcnts.cpp [AMDGPU][Waitcnt] Re-apply fix "comparison of integers of different signs" build error" 2018-07-16 10:21:36 +00:00
SIInstrFormats.td AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SIInstrInfo.cpp [PSV] Update API to be able to use TargetCustom without UB. 2018-08-20 19:23:45 +00:00
SIInstrInfo.h [PSV] Update API to be able to use TargetCustom without UB. 2018-08-20 19:23:45 +00:00
SIInstrInfo.td [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
SIInstructions.td AMDGPU: Fix packing undef parts of build_vector 2018-08-12 08:42:46 +00:00
SIIntrinsics.td
…
SILoadStoreOptimizer.cpp [MI] Change the array of `MachineMemOperand` pointers to be 2018-08-16 21:30:05 +00:00
SILowerControlFlow.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SILowerI1Copies.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SIMachineFunctionInfo.cpp Reapply "AMDGPU: Fix handling of alignment padding in DAG argument lowering" 2018-07-20 09:05:08 +00:00
SIMachineFunctionInfo.h AMDGPU/AMDHSA: Remove GridWorkGroupCountX/Y/Z 2018-06-21 18:36:04 +00:00
SIMachineScheduler.cpp AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers 2018-05-22 02:03:23 +00:00
SIMachineScheduler.h Remove \brief commands from doxygen comments. 2018-05-01 15:54:18 +00:00
SIMemoryLegalizer.cpp run post-RA hazard recognizer pass late 2018-07-16 10:02:41 +00:00
SIOptimizeExecMasking.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SIOptimizeExecMaskingPreRA.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SIPeepholeSDWA.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SIProgramInfo.h [AMDGPU] Refactor HSAMetadataStream::emitKernel (NFC) 2018-07-10 17:31:32 +00:00
SIRegisterInfo.cpp [MI] Change the array of `MachineMemOperand` pointers to be 2018-08-16 21:30:05 +00:00
SIRegisterInfo.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SIRegisterInfo.td AMDGPU: Make v4i16/v4f16 legal 2018-06-15 15:15:46 +00:00
SISchedule.td [SchedModel] Complete models shouldn't match against itineraries when they don't use them (PR35639) 2018-04-05 13:11:36 +00:00
SIShrinkInstructions.cpp AMDGPU: Use existing function to check for VGPRs 2018-07-20 21:20:36 +00:00
SIWholeQuadMode.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SMInstructions.td [AMDGPU][MC][VI][GFX9] Added s_atc_probe* instructions 2018-04-06 15:48:39 +00:00
SOPInstructions.td [AMDGPU][MC][GFX9] Added instructions s_mul_hi_*32, s_lshl*_add_u32 2018-04-09 13:10:33 +00:00
VIInstrFormats.td
…
VIInstructions.td
…
VOP1Instructions.td [AMDGPU] Convert rcp to rcp_iflag 2018-06-27 15:33:33 +00:00
VOP2Instructions.td AMDGPU: Improve hack for packing conversion ops 2018-08-01 20:13:58 +00:00
VOP3Instructions.td AMDGPU: Remove broken i16 ternary patterns 2018-08-07 21:54:37 +00:00
VOP3PInstructions.td AMDGPU: Add clamp bit to dot intrinsics 2018-08-01 01:31:30 +00:00
VOPCInstructions.td AMDGPU: Implement llvm.amdgcn.icmp/fcmp for i16/f16 2018-08-15 21:25:20 +00:00
VOPInstructions.td AMDGPU: Introduce common SOP_Pseudo and VOP_Pseudo TableGen base classes 2018-03-26 13:56:53 +00:00