llvm-project/llvm/test/CodeGen/MIR
Jay Foad 479145a5c2 [AMDGPU] Avoid hard-coded line numbers in error message checks
This makes it easier for us to maintain downstream changes to some of
these tests. NFC.

Differential Revision: https://reviews.llvm.org/D78716
2020-04-23 21:06:09 +01:00
..
AArch64 [llvm][MIRVRegNamer] Avoid collisions across jump table indices. 2020-04-22 14:58:44 -04:00
AMDGPU [AMDGPU] Avoid hard-coded line numbers in error message checks 2020-04-23 21:06:09 +01:00
ARM [ARM] Track epilogue instructions with FrameDestroy flag (NFC) 2020-03-18 13:32:59 +00:00
Generic [llvm][MIRVRegNamerUtils] Adding hashing on CImm / FPImm MachineOperands. 2019-12-16 18:25:04 -05:00
Hexagon Reland D73534: [DebugInfo] Enable the debug entry values feature by default 2020-03-19 13:57:30 +01:00
Mips [MIParser] Set RegClassOrRegBank during instruction parsing 2019-10-22 14:25:37 +00:00
NVPTX
PowerPC [PowerPC][NFC] Move codegen tests to PowerPC from MIR/PowerPC 2019-09-13 14:18:36 +00:00
WebAssembly [WebAssembly] Fix tests missed in rL374235 2019-10-09 23:06:38 +00:00
X86 [X86] Clean up some mir tests with INLINEASM to avoid regdef or to correct the immediate for the regdef. 2020-04-17 21:55:44 -07:00
README

README

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.