forked from OSchip/llvm-project
114 lines
3.6 KiB
C++
114 lines
3.6 KiB
C++
//- WebAssemblyISelDAGToDAG.cpp - A dag to dag inst selector for WebAssembly -//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief This file defines an instruction selector for the WebAssembly target.
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///
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "WebAssembly.h"
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#include "WebAssemblyTargetMachine.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/IR/Function.h" // To access function attributes.
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/KnownBits.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-isel"
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//===--------------------------------------------------------------------===//
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/// WebAssembly-specific code to select WebAssembly machine instructions for
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/// SelectionDAG operations.
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///
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namespace {
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class WebAssemblyDAGToDAGISel final : public SelectionDAGISel {
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/// Keep a pointer to the WebAssemblySubtarget around so that we can make the
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/// right decision when generating code for different targets.
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const WebAssemblySubtarget *Subtarget;
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bool ForCodeSize;
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public:
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WebAssemblyDAGToDAGISel(WebAssemblyTargetMachine &tm,
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CodeGenOpt::Level OptLevel)
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: SelectionDAGISel(tm, OptLevel), Subtarget(nullptr), ForCodeSize(false) {
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}
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StringRef getPassName() const override {
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return "WebAssembly Instruction Selection";
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}
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bool runOnMachineFunction(MachineFunction &MF) override {
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ForCodeSize = MF.getFunction().hasFnAttribute(Attribute::OptimizeForSize) ||
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MF.getFunction().hasFnAttribute(Attribute::MinSize);
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Subtarget = &MF.getSubtarget<WebAssemblySubtarget>();
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return SelectionDAGISel::runOnMachineFunction(MF);
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}
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void Select(SDNode *Node) override;
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bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
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std::vector<SDValue> &OutOps) override;
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// Include the pieces autogenerated from the target description.
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#include "WebAssemblyGenDAGISel.inc"
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private:
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// add select functions here...
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};
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} // end anonymous namespace
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void WebAssemblyDAGToDAGISel::Select(SDNode *Node) {
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// If we have a custom node, we already have selected!
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if (Node->isMachineOpcode()) {
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DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
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Node->setNodeId(-1);
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return;
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}
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// Few custom selection stuff.
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EVT VT = Node->getValueType(0);
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switch (Node->getOpcode()) {
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default:
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break;
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// If we need WebAssembly-specific selection, it would go here.
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(void)VT;
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}
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// Select the default instruction.
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SelectCode(Node);
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}
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bool WebAssemblyDAGToDAGISel::SelectInlineAsmMemoryOperand(
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const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
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switch (ConstraintID) {
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case InlineAsm::Constraint_i:
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case InlineAsm::Constraint_m:
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// We just support simple memory operands that just have a single address
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// operand and need no special handling.
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OutOps.push_back(Op);
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return false;
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default:
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break;
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}
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return true;
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}
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/// This pass converts a legalized DAG into a WebAssembly-specific DAG, ready
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/// for instruction scheduling.
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FunctionPass *llvm::createWebAssemblyISelDag(WebAssemblyTargetMachine &TM,
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CodeGenOpt::Level OptLevel) {
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return new WebAssemblyDAGToDAGISel(TM, OptLevel);
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}
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