forked from OSchip/llvm-project
118 lines
5.0 KiB
YAML
118 lines
5.0 KiB
YAML
# RUN: llc -o - %s -start-after=if-converter | FileCheck %s
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--- |
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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%struct.rwlock_t.0.22.58.68.242.244 = type {}
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@tasklist_lock = external global %struct.rwlock_t.0.22.58.68.242.244, align 1
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; Function Attrs: nounwind
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define void @mm_update_next_owner(i8** %p1, i32* %p2) #0 {
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entry:
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%0 = load i8*, i8** %p1, align 8
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br i1 undef, label %do.body.92, label %for.body.21
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for.body.21: ; preds = %entry
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unreachable
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do.body.92: ; preds = %entry
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%usage = getelementptr inbounds i8, i8* %0, i64 -48
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%counter.i = bitcast i8* %usage to i32*
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%call95 = tail call signext i32 bitcast (i32 (...)* @__raw_read_unlock to i32 (%struct.rwlock_t.0.22.58.68.242.244*)*)(%struct.rwlock_t.0.22.58.68.242.244* nonnull @tasklist_lock) #1
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store volatile i32 0, i32* %p2, align 4
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tail call void asm sideeffect "#compiler barrier", "~{memory}"() #1
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%1 = tail call i32 asm sideeffect "\0Alwsync \0A1:\09lwarx\09$0,0,$1\09\09# atomic_dec_return\0A\09addic\09$0,$0,-1\0A\09stwcx.\09$0,0,$1\0A\09bne-\091b\0Async \0A", "=&r,r,~{cc},~{xer},~{memory}"(i32* %counter.i) #1
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%cmp.i = icmp eq i32 %1, 0
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br i1 %cmp.i, label %if.then.i, label %put_task_struct.exit
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if.then.i: ; preds = %do.body.92
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unreachable
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put_task_struct.exit: ; preds = %do.body.92
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ret void
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}
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declare signext i32 @__raw_read_unlock(...)
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attributes #0 = { nounwind "target-cpu"="pwr7" }
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attributes #1 = { nounwind }
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...
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---
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name: mm_update_next_owner
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alignment: 4
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exposesReturnsTwice: false
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hasInlineAsm: true
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isSSA: false
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tracksRegLiveness: true
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tracksSubRegLiveness: false
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liveins:
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- { reg: '%x3' }
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- { reg: '%x4' }
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calleeSavedRegisters: [ '%cr2', '%cr3', '%cr4', '%f14', '%f15', '%f16',
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'%f17', '%f18', '%f19', '%f20', '%f21', '%f22',
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'%f23', '%f24', '%f25', '%f26', '%f27', '%f28',
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'%f29', '%f30', '%f31', '%r14', '%r15', '%r16',
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'%r17', '%r18', '%r19', '%r20', '%r21', '%r22',
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'%r23', '%r24', '%r25', '%r26', '%r27', '%r28',
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'%r29', '%r30', '%r31', '%v20', '%v21', '%v22',
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'%v23', '%v24', '%v25', '%v26', '%v27', '%v28',
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'%v29', '%v30', '%v31', '%vf20', '%vf21', '%vf22',
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'%vf23', '%vf24', '%vf25', '%vf26', '%vf27', '%vf28',
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'%vf29', '%vf30', '%vf31', '%x14', '%x15', '%x16',
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'%x17', '%x18', '%x19', '%x20', '%x21', '%x22',
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'%x23', '%x24', '%x25', '%x26', '%x27', '%x28',
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'%x29', '%x30', '%x31', '%cr2eq', '%cr3eq', '%cr4eq',
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'%cr2gt', '%cr3gt', '%cr4gt', '%cr2lt', '%cr3lt',
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'%cr4lt', '%cr2un', '%cr3un', '%cr4un' ]
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 144
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: true
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hasCalls: true
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maxCallFrameSize: 112
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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fixedStack:
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- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%x30' }
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- { id: 1, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '%x29' }
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body: |
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bb.0.entry:
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liveins: %x3, %x4, %x29, %x30, %x29, %x30
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%x0 = MFLR8 implicit %lr8
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STD %x0, 16, %x1
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%x1 = STDU %x1, -144, %x1
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STD killed %x29, 120, %x1 :: (store 8 into %fixed-stack.1)
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STD killed %x30, 128, %x1 :: (store 8 into %fixed-stack.0, align 16)
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%x30 = OR8 %x4, %x4
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%x3 = LD 0, killed %x3 :: (load 8 from %ir.p1)
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%x29 = ADDI8 killed %x3, -48
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%x3 = ADDIStocHA %x2, @tasklist_lock
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%x3 = LDtocL @tasklist_lock, killed %x3, implicit %x2 :: (load 8 from got)
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BL8_NOP @__raw_read_unlock, csr_svr464_altivec, implicit-def %lr8, implicit %rm, implicit %x3, implicit %x2, implicit-def %r1, implicit-def dead %x3
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%r3 = LI 0
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STW killed %r3, 0, killed %x30 :: (volatile store 4 into %ir.p2)
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INLINEASM $"#compiler barrier", 25
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INLINEASM $"\0Alwsync \0A1:\09lwarx\09$0,0,$1\09\09# atomic_dec_return\0A\09addic\09$0,$0,-1\0A\09stwcx.\09$0,0,$1\0A\09bne-\091b\0Async \0A", 25, 131083, def early-clobber %r3, 851977, killed %x29, 12, implicit-def dead early-clobber %cr0
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; CHECK-LABEL: @mm_update_next_owner
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; CHECK-NOT: lwarx 29, 0, 29
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; CHECK-NOT: stwcx. 29, 0, 29
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%cr0 = CMPLWI killed %r3, 0
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%x30 = LD 128, %x1 :: (load 8 from %fixed-stack.0, align 16)
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%x29 = LD 120, %x1 :: (load 8 from %fixed-stack.1)
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%x1 = ADDI8 %x1, 144
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%x0 = LD 16, %x1
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MTLR8 %x0, implicit-def %lr8
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BLR8 implicit %lr8, implicit %rm
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...
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