forked from OSchip/llvm-project
267 lines
8.6 KiB
LLVM
267 lines
8.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE42
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX,AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
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declare i32 @llvm.x86.sse.movmsk.ps(<4 x float>)
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declare i32 @llvm.x86.sse2.movmsk.pd(<2 x double>)
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declare i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8>)
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; Use widest possible vector for movmsk comparisons (PR37087)
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define i1 @movmskps_noneof_bitcast_v2f64(<2 x double> %a0) {
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; SSE-LABEL: movmskps_noneof_bitcast_v2f64:
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; SSE: # %bb.0:
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; SSE-NEXT: xorpd %xmm1, %xmm1
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; SSE-NEXT: cmpeqpd %xmm0, %xmm1
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; SSE-NEXT: movmskpd %xmm1, %eax
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; SSE-NEXT: testl %eax, %eax
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; SSE-NEXT: sete %al
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; SSE-NEXT: retq
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;
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; AVX-LABEL: movmskps_noneof_bitcast_v2f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vcmpeqpd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vmovmskpd %xmm0, %eax
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; AVX-NEXT: testl %eax, %eax
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; AVX-NEXT: sete %al
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; AVX-NEXT: retq
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%1 = fcmp oeq <2 x double> zeroinitializer, %a0
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%2 = sext <2 x i1> %1 to <2 x i64>
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%3 = bitcast <2 x i64> %2 to <4 x float>
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%4 = tail call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %3)
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%5 = icmp eq i32 %4, 0
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ret i1 %5
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}
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define i1 @movmskps_allof_bitcast_v2f64(<2 x double> %a0) {
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; SSE-LABEL: movmskps_allof_bitcast_v2f64:
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; SSE: # %bb.0:
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; SSE-NEXT: xorpd %xmm1, %xmm1
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; SSE-NEXT: cmpeqpd %xmm0, %xmm1
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; SSE-NEXT: movmskpd %xmm1, %eax
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; SSE-NEXT: cmpl $3, %eax
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; SSE-NEXT: sete %al
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; SSE-NEXT: retq
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;
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; AVX-LABEL: movmskps_allof_bitcast_v2f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vcmpeqpd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vmovmskpd %xmm0, %eax
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; AVX-NEXT: cmpl $3, %eax
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; AVX-NEXT: sete %al
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; AVX-NEXT: retq
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%1 = fcmp oeq <2 x double> zeroinitializer, %a0
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%2 = sext <2 x i1> %1 to <2 x i64>
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%3 = bitcast <2 x i64> %2 to <4 x float>
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%4 = tail call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %3)
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%5 = icmp eq i32 %4, 15
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ret i1 %5
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}
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define i1 @pmovmskb_noneof_bitcast_v2i64(<2 x i64> %a0) {
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; SSE2-LABEL: pmovmskb_noneof_bitcast_v2i64:
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; SSE2: # %bb.0:
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; SSE2-NEXT: pxor %xmm1, %xmm1
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; SSE2-NEXT: pcmpgtd %xmm0, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3]
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; SSE2-NEXT: movmskps %xmm0, %eax
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; SSE2-NEXT: testl %eax, %eax
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; SSE2-NEXT: sete %al
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; SSE2-NEXT: retq
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;
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; SSE42-LABEL: pmovmskb_noneof_bitcast_v2i64:
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; SSE42: # %bb.0:
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; SSE42-NEXT: movmskpd %xmm0, %eax
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; SSE42-NEXT: testl %eax, %eax
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; SSE42-NEXT: sete %al
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; SSE42-NEXT: retq
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;
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; AVX-LABEL: pmovmskb_noneof_bitcast_v2i64:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovmskpd %xmm0, %eax
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; AVX-NEXT: testl %eax, %eax
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; AVX-NEXT: sete %al
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; AVX-NEXT: retq
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%1 = icmp sgt <2 x i64> zeroinitializer, %a0
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%2 = sext <2 x i1> %1 to <2 x i64>
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%3 = bitcast <2 x i64> %2 to <16 x i8>
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%4 = tail call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> %3)
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%5 = icmp eq i32 %4, 0
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ret i1 %5
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}
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define i1 @pmovmskb_allof_bitcast_v2i64(<2 x i64> %a0) {
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; SSE2-LABEL: pmovmskb_allof_bitcast_v2i64:
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; SSE2: # %bb.0:
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; SSE2-NEXT: pxor %xmm1, %xmm1
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; SSE2-NEXT: pcmpgtd %xmm0, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3]
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; SSE2-NEXT: movmskps %xmm0, %eax
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; SSE2-NEXT: cmpl $15, %eax
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; SSE2-NEXT: sete %al
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; SSE2-NEXT: retq
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;
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; SSE42-LABEL: pmovmskb_allof_bitcast_v2i64:
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; SSE42: # %bb.0:
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; SSE42-NEXT: movmskpd %xmm0, %eax
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; SSE42-NEXT: cmpl $3, %eax
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; SSE42-NEXT: sete %al
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; SSE42-NEXT: retq
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;
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; AVX-LABEL: pmovmskb_allof_bitcast_v2i64:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovmskpd %xmm0, %eax
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; AVX-NEXT: cmpl $3, %eax
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; AVX-NEXT: sete %al
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; AVX-NEXT: retq
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%1 = icmp sgt <2 x i64> zeroinitializer, %a0
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%2 = sext <2 x i1> %1 to <2 x i64>
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%3 = bitcast <2 x i64> %2 to <16 x i8>
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%4 = tail call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> %3)
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%5 = icmp eq i32 %4, 65535
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ret i1 %5
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}
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define i1 @pmovmskb_noneof_bitcast_v4f32(<4 x float> %a0) {
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; SSE-LABEL: pmovmskb_noneof_bitcast_v4f32:
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; SSE: # %bb.0:
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; SSE-NEXT: xorps %xmm1, %xmm1
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; SSE-NEXT: cmpeqps %xmm0, %xmm1
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; SSE-NEXT: movmskps %xmm1, %eax
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; SSE-NEXT: testl %eax, %eax
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; SSE-NEXT: sete %al
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; SSE-NEXT: retq
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;
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; AVX-LABEL: pmovmskb_noneof_bitcast_v4f32:
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; AVX: # %bb.0:
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; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vcmpeqps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vmovmskps %xmm0, %eax
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; AVX-NEXT: testl %eax, %eax
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; AVX-NEXT: sete %al
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; AVX-NEXT: retq
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%1 = fcmp oeq <4 x float> %a0, zeroinitializer
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%2 = sext <4 x i1> %1 to <4 x i32>
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%3 = bitcast <4 x i32> %2 to <16 x i8>
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%4 = tail call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> %3)
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%5 = icmp eq i32 %4, 0
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ret i1 %5
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}
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define i1 @pmovmskb_allof_bitcast_v4f32(<4 x float> %a0) {
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; SSE-LABEL: pmovmskb_allof_bitcast_v4f32:
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; SSE: # %bb.0:
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; SSE-NEXT: xorps %xmm1, %xmm1
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; SSE-NEXT: cmpeqps %xmm0, %xmm1
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; SSE-NEXT: movmskps %xmm1, %eax
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; SSE-NEXT: cmpl $15, %eax
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; SSE-NEXT: sete %al
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; SSE-NEXT: retq
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;
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; AVX-LABEL: pmovmskb_allof_bitcast_v4f32:
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; AVX: # %bb.0:
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; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vcmpeqps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vmovmskps %xmm0, %eax
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; AVX-NEXT: cmpl $15, %eax
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; AVX-NEXT: sete %al
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; AVX-NEXT: retq
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%1 = fcmp oeq <4 x float> %a0, zeroinitializer
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%2 = sext <4 x i1> %1 to <4 x i32>
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%3 = bitcast <4 x i32> %2 to <16 x i8>
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%4 = tail call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> %3)
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%5 = icmp eq i32 %4, 65535
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ret i1 %5
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}
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; AND(MOVMSK(X),MOVMSK(Y)) -> MOVMSK(AND(X,Y))
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; XOR(MOVMSK(X),MOVMSK(Y)) -> MOVMSK(XOR(X,Y))
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; OR(MOVMSK(X),MOVMSK(Y)) -> MOVMSK(OR(X,Y))
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; if the elements are the same width.
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define i32 @and_movmskpd_movmskpd(<2 x double> %a0, <2 x i64> %a1) {
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; SSE-LABEL: and_movmskpd_movmskpd:
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; SSE: # %bb.0:
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; SSE-NEXT: xorpd %xmm2, %xmm2
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; SSE-NEXT: cmpeqpd %xmm0, %xmm2
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; SSE-NEXT: andpd %xmm1, %xmm2
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; SSE-NEXT: movmskpd %xmm2, %eax
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; SSE-NEXT: retq
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;
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; AVX-LABEL: and_movmskpd_movmskpd:
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; AVX: # %bb.0:
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; AVX-NEXT: vxorpd %xmm2, %xmm2, %xmm2
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; AVX-NEXT: vcmpeqpd %xmm0, %xmm2, %xmm0
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; AVX-NEXT: vandpd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vmovmskpd %xmm0, %eax
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; AVX-NEXT: retq
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%1 = fcmp oeq <2 x double> zeroinitializer, %a0
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%2 = sext <2 x i1> %1 to <2 x i64>
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%3 = bitcast <2 x i64> %2 to <2 x double>
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%4 = tail call i32 @llvm.x86.sse2.movmsk.pd(<2 x double> %3)
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%5 = icmp sgt <2 x i64> zeroinitializer, %a1
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%6 = bitcast <2 x i1> %5 to i2
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%7 = zext i2 %6 to i32
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%8 = and i32 %4, %7
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ret i32 %8
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}
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define i32 @xor_movmskps_movmskps(<4 x float> %a0, <4 x i32> %a1) {
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; SSE-LABEL: xor_movmskps_movmskps:
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; SSE: # %bb.0:
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; SSE-NEXT: xorps %xmm2, %xmm2
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; SSE-NEXT: cmpeqps %xmm0, %xmm2
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; SSE-NEXT: xorps %xmm1, %xmm2
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; SSE-NEXT: movmskps %xmm2, %eax
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; SSE-NEXT: retq
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;
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; AVX-LABEL: xor_movmskps_movmskps:
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; AVX: # %bb.0:
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; AVX-NEXT: vxorps %xmm2, %xmm2, %xmm2
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; AVX-NEXT: vcmpeqps %xmm0, %xmm2, %xmm0
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; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vmovmskps %xmm0, %eax
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; AVX-NEXT: retq
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%1 = fcmp oeq <4 x float> zeroinitializer, %a0
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%2 = sext <4 x i1> %1 to <4 x i32>
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%3 = bitcast <4 x i32> %2 to <4 x float>
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%4 = tail call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %3)
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%5 = ashr <4 x i32> %a1, <i32 31, i32 31, i32 31, i32 31>
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%6 = bitcast <4 x i32> %5 to <4 x float>
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%7 = tail call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %6)
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%8 = xor i32 %4, %7
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ret i32 %8
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}
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define i32 @or_pmovmskb_pmovmskb(<16 x i8> %a0, <8 x i16> %a1) {
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; SSE-LABEL: or_pmovmskb_pmovmskb:
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; SSE: # %bb.0:
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; SSE-NEXT: pxor %xmm2, %xmm2
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; SSE-NEXT: pcmpeqb %xmm0, %xmm2
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; SSE-NEXT: psraw $15, %xmm1
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; SSE-NEXT: por %xmm2, %xmm1
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; SSE-NEXT: pmovmskb %xmm1, %eax
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; SSE-NEXT: retq
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;
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; AVX-LABEL: or_pmovmskb_pmovmskb:
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; AVX: # %bb.0:
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; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm0
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; AVX-NEXT: vpsraw $15, %xmm1, %xmm1
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; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpmovmskb %xmm0, %eax
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; AVX-NEXT: retq
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%1 = icmp eq <16 x i8> zeroinitializer, %a0
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%2 = sext <16 x i1> %1 to <16 x i8>
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%3 = tail call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> %2)
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%4 = ashr <8 x i16> %a1, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
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%5 = bitcast <8 x i16> %4 to <16 x i8>
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%6 = tail call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> %5)
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%7 = or i32 %3, %6
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ret i32 %7
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}
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