forked from OSchip/llvm-project
199 lines
5.5 KiB
YAML
199 lines
5.5 KiB
YAML
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL
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--- |
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define i64 @test_add_i64(i64 %arg1, i64 %arg2) {
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%ret = add i64 %arg1, %arg2
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ret i64 %ret
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}
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define i32 @test_add_i32(i32 %arg1, i32 %arg2) {
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%ret = add i32 %arg1, %arg2
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ret i32 %ret
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}
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define i16 @test_add_i16(i16 %arg1, i16 %arg2) {
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%ret = add i16 %arg1, %arg2
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ret i16 %ret
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}
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define i8 @test_add_i8(i8 %arg1, i8 %arg2) {
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%ret = add i8 %arg1, %arg2
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ret i8 %ret
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}
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define <4 x i32> @test_add_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {
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%ret = add <4 x i32> %arg1, %arg2
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ret <4 x i32> %ret
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}
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define <4 x float> @test_add_v4f32(<4 x float> %arg1, <4 x float> %arg2) {
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%ret = fadd <4 x float> %arg1, %arg2
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ret <4 x float> %ret
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}
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...
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---
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name: test_add_i64
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# ALL-LABEL: name: test_add_i64
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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# ALL: %0:gr64 = COPY $rdi
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# ALL-NEXT: %1:gr64 = COPY $rsi
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# ALL-NEXT: %2:gr64 = ADD64rr %0, %1
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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%0(s64) = COPY $rdi
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%1(s64) = COPY $rsi
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%2(s64) = G_ADD %0, %1
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$rax = COPY %2(s64)
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...
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---
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name: test_add_i32
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# ALL-LABEL: name: test_add_i32
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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# ALL: %0:gr32 = COPY $edi
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# ALL-NEXT: %1:gr32 = COPY $esi
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# ALL-NEXT: %2:gr32 = ADD32rr %0, %1
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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%0(s32) = COPY $edi
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%1(s32) = COPY $esi
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%2(s32) = G_ADD %0, %1
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$eax = COPY %2(s32)
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...
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---
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name: test_add_i16
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# ALL-LABEL: name: test_add_i16
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alignment: 16
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legalized: true
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regBankSelected: true
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selected: false
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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# ALL: %0:gr16 = COPY $di
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# ALL: %1:gr16 = COPY $si
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# ALL: %2:gr16 = ADD16rr %0, %1, implicit-def $eflags
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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%0(s16) = COPY $di
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%1(s16) = COPY $si
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%2(s16) = G_ADD %0, %1
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$ax = COPY %2(s16)
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RET 0, implicit $ax
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...
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---
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name: test_add_i8
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# ALL-LABEL: name: test_add_i8
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alignment: 16
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legalized: true
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regBankSelected: true
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selected: false
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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# ALL: %0:gr8 = COPY $dil
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# ALL: %1:gr8 = COPY $sil
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# ALL: %2:gr8 = ADD8rr %0, %1, implicit-def $eflags
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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%0(s8) = COPY $dil
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%1(s8) = COPY $sil
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%2(s8) = G_ADD %0, %1
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$al = COPY %2(s8)
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RET 0, implicit $al
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...
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---
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name: test_add_v4i32
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# ALL-LABEL: name: test_add_v4i32
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alignment: 16
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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# NO_AVX512VL: %0:vr128 = COPY $xmm0
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# NO_AVX512VL: %1:vr128 = COPY $xmm1
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# SSE-NEXT: %2:vr128 = PADDDrr %0, %1
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# AVX-NEXT: %2:vr128 = VPADDDrr %0, %1
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# AVX512F-NEXT: %2:vr128 = VPADDDrr %0, %1
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# AVX512VL: %0:vr128x = COPY $xmm0
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# AVX512VL: %1:vr128x = COPY $xmm1
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# AVX512VL-NEXT: %2:vr128x = VPADDDZ128rr %0, %1
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body: |
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bb.1 (%ir-block.0):
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liveins: $xmm0, $xmm1
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%0(<4 x s32>) = COPY $xmm0
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%1(<4 x s32>) = COPY $xmm1
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%2(<4 x s32>) = G_ADD %0, %1
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$xmm0 = COPY %2(<4 x s32>)
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RET 0, implicit $xmm0
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...
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---
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name: test_add_v4f32
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# ALL-LABEL: name: test_add_v4f32
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alignment: 16
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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# SSE: %0:vr128 = COPY $xmm0
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# SSE-NEXT: %1:vr128 = COPY $xmm1
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# SSE-NEXT: %2:vr128 = nofpexcept ADDPSrr %0, %1
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# AVX: %0:vr128 = COPY $xmm0
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# AVX-NEXT: %1:vr128 = COPY $xmm1
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# AVX-NEXT: %2:vr128 = nofpexcept VADDPSrr %0, %1
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# AVX512F: %0:vr128 = COPY $xmm0
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# AVX512F-NEXT: 1:vr128 = COPY $xmm1
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# AVX512F-NEXT: %2:vr128 = nofpexcept VADDPSrr %0, %1
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# AVX512VL: %0:vr128x = COPY $xmm0
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# AVX512VL-NEXT: %1:vr128x = COPY $xmm1
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# AVX512VL-NEXT: %2:vr128x = nofpexcept VADDPSZ128rr %0, %1
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body: |
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bb.1 (%ir-block.0):
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liveins: $xmm0, $xmm1
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%0(<4 x s32>) = COPY $xmm0
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%1(<4 x s32>) = COPY $xmm1
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%2(<4 x s32>) = G_FADD %0, %1
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$xmm0 = COPY %2(<4 x s32>)
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RET 0, implicit $xmm0
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...
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