llvm-project/llvm/test/CodeGen/X86/GlobalISel/legalize-insert-vec512.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
--- |
define void @test_insert_128() {
ret void
}
define void @test_insert_256() {
ret void
}
...
---
name: test_insert_128
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $zmm0, $ymm1
; ALL-LABEL: name: test_insert_128
; ALL: [[COPY:%[0-9]+]]:_(<16 x s32>) = COPY $zmm0
; ALL: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $xmm1
; ALL: [[INSERT:%[0-9]+]]:_(<16 x s32>) = G_INSERT [[COPY]], [[COPY1]](<4 x s32>), 0
; ALL: $zmm0 = COPY [[INSERT]](<16 x s32>)
; ALL: RET 0, implicit $ymm0
%0(<16 x s32>) = COPY $zmm0
%1(<4 x s32>) = COPY $xmm1
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 0
$zmm0 = COPY %2(<16 x s32>)
RET 0, implicit $ymm0
...
---
name: test_insert_256
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $zmm0, $ymm1
; ALL-LABEL: name: test_insert_256
; ALL: [[COPY:%[0-9]+]]:_(<16 x s32>) = COPY $zmm0
; ALL: [[COPY1:%[0-9]+]]:_(<8 x s32>) = COPY $ymm1
; ALL: [[INSERT:%[0-9]+]]:_(<16 x s32>) = G_INSERT [[COPY]], [[COPY1]](<8 x s32>), 0
; ALL: $zmm0 = COPY [[INSERT]](<16 x s32>)
; ALL: RET 0, implicit $ymm0
%0(<16 x s32>) = COPY $zmm0
%1(<8 x s32>) = COPY $ymm1
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 0
$zmm0 = COPY %2(<16 x s32>)
RET 0, implicit $ymm0
...