maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/MIR
History
Djordje Todorovic 5aa5c943f7 Reland "[DebugInfo] Enable the debug entry values feature by default" 
Differential Revision: https://reviews.llvm.org/D73534
 		2020-03-10 09:15:06 +01:00
..
AArch64 [llvm][MIRVRegNamer] Avoid collisions across constant pool indices. 2020-03-10 01:13:20 -04:00
AMDGPU AMDGPU: Split denormal mode tracking bits 2020-02-04 10:44:21 -08:00
ARM Revert "[ARM] Add CPSR as an implicit use of t2IT" 2020-02-27 15:43:44 +00:00
Generic [llvm][MIRVRegNamerUtils] Adding hashing on CImm / FPImm MachineOperands. 2019-12-16 18:25:04 -05:00
Hexagon Reland "[DebugInfo] Enable the debug entry values feature by default" 2020-03-10 09:15:06 +01:00
Mips [MIParser] Set RegClassOrRegBank during instruction parsing 2019-10-22 14:25:37 +00:00
NVPTX
…
PowerPC [PowerPC][NFC] Move codegen tests to PowerPC from MIR/PowerPC 2019-09-13 14:18:36 +00:00
WebAssembly [WebAssembly] Fix tests missed in rL374235 2019-10-09 23:06:38 +00:00
X86 Reland "[DebugInfo] Enable the debug entry values feature by default" 2020-03-10 09:15:06 +01:00
README
…

README 

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.