forked from OSchip/llvm-project
265 lines
9.5 KiB
C++
265 lines
9.5 KiB
C++
//===- ARM64.cpp ----------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "InputFiles.h"
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#include "Symbols.h"
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#include "SyntheticSections.h"
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#include "Target.h"
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#include "lld/Common/ErrorHandler.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/BinaryFormat/MachO.h"
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#include "llvm/Support/Endian.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm::MachO;
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using namespace llvm::support::endian;
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using namespace lld;
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using namespace lld::macho;
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namespace {
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struct ARM64 : TargetInfo {
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ARM64();
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uint64_t getEmbeddedAddend(MemoryBufferRef, const section_64 &,
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const relocation_info) const override;
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void relocateOne(uint8_t *loc, const Reloc &, uint64_t va,
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uint64_t pc) const override;
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void writeStub(uint8_t *buf, const macho::Symbol &) const override;
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void writeStubHelperHeader(uint8_t *buf) const override;
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void writeStubHelperEntry(uint8_t *buf, const DylibSymbol &,
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uint64_t entryAddr) const override;
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void relaxGotLoad(uint8_t *loc, uint8_t type) const override;
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const TargetInfo::RelocAttrs &getRelocAttrs(uint8_t type) const override;
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uint64_t getPageSize() const override { return 16 * 1024; }
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};
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} // namespace
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// Random notes on reloc types:
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// ADDEND always pairs with BRANCH26, PAGE21, or PAGEOFF12
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// SUBTRACTOR always pairs with UNSIGNED (a delta between two sections)
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// POINTER_TO_GOT: 4-byte is pc-relative, 8-byte is absolute
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const TargetInfo::RelocAttrs &ARM64::getRelocAttrs(uint8_t type) const {
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static const std::array<TargetInfo::RelocAttrs, 11> relocAttrsArray{{
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#define B(x) RelocAttrBits::x
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{"UNSIGNED", B(ABSOLUTE) | B(EXTERN) | B(LOCAL) | B(TLV) | B(DYSYM8) |
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B(BYTE4) | B(BYTE8)},
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{"SUBTRACTOR", B(SUBTRAHEND) | B(BYTE8)},
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{"BRANCH26", B(PCREL) | B(EXTERN) | B(BRANCH) | B(BYTE4)},
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{"PAGE21", B(PCREL) | B(EXTERN) | B(BYTE4)},
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{"PAGEOFF12", B(ABSOLUTE) | B(EXTERN) | B(BYTE4)},
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{"GOT_LOAD_PAGE21", B(PCREL) | B(EXTERN) | B(GOT) | B(BYTE4)},
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{"GOT_LOAD_PAGEOFF12",
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B(ABSOLUTE) | B(EXTERN) | B(GOT) | B(LOAD) | B(BYTE4)},
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{"POINTER_TO_GOT", B(PCREL) | B(EXTERN) | B(GOT) | B(BYTE4) | B(BYTE8)},
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{"TLVP_LOAD_PAGE21", B(PCREL) | B(EXTERN) | B(TLV) | B(BYTE4)},
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{"TLVP_LOAD_PAGEOFF12",
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B(ABSOLUTE) | B(EXTERN) | B(TLV) | B(LOAD) | B(BYTE4)},
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{"ADDEND", B(ADDEND)},
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#undef B
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}};
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assert(type >= 0 && type < relocAttrsArray.size() &&
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"invalid relocation type");
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if (type < 0 || type >= relocAttrsArray.size())
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return TargetInfo::invalidRelocAttrs;
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return relocAttrsArray[type];
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}
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uint64_t ARM64::getEmbeddedAddend(MemoryBufferRef mb, const section_64 &sec,
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const relocation_info rel) const {
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// TODO(gkm): extract embedded addend just so we can assert that it is 0
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return 0;
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}
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inline uint64_t bitField(uint64_t value, int right, int width, int left) {
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return ((value >> right) & ((1 << width) - 1)) << left;
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}
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// 25 0
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// +-----------+---------------------------------------------------+
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// | | imm26 |
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// +-----------+---------------------------------------------------+
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inline uint64_t encodeBranch26(uint64_t base, uint64_t va) {
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// Since branch destinations are 4-byte aligned, the 2 least-
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// significant bits are 0. They are right shifted off the end.
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return (base | bitField(va, 2, 26, 0));
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}
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// 30 29 23 5
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// +-+---+---------+-------------------------------------+---------+
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// | |ilo| | immhi | |
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// +-+---+---------+-------------------------------------+---------+
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inline uint64_t encodePage21(uint64_t base, uint64_t va) {
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return (base | bitField(va, 12, 2, 29) | bitField(va, 14, 19, 5));
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}
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// 21 10
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// +-------------------+-----------------------+-------------------+
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// | | imm12 | |
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// +-------------------+-----------------------+-------------------+
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inline uint64_t encodePageOff12(uint64_t base, uint64_t va) {
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int scale = ((base & 0x3b000000) == 0x39000000) ? base >> 30 : 0;
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// TODO(gkm): extract embedded addend and warn if != 0
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// uint64_t addend = ((base & 0x003FFC00) >> 10);
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return (base | bitField(va, scale, 12 - scale, 10));
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}
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inline uint64_t pageBits(uint64_t address) {
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const uint64_t pageMask = ~0xfffull;
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return address & pageMask;
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}
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// For instruction relocations (load, store, add), the base
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// instruction is pre-populated in the text section. A pre-populated
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// instruction has opcode & register-operand bits set, with immediate
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// operands zeroed. We read it from text, OR-in the immediate
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// operands, then write-back the completed instruction.
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void ARM64::relocateOne(uint8_t *loc, const Reloc &r, uint64_t value,
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uint64_t pc) const {
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uint32_t base = ((r.length == 2) ? read32le(loc) : 0);
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value += r.addend;
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switch (r.type) {
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case ARM64_RELOC_BRANCH26:
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value = encodeBranch26(base, value - pc);
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break;
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case ARM64_RELOC_UNSIGNED:
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break;
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case ARM64_RELOC_POINTER_TO_GOT:
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if (r.pcrel)
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value -= pc;
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break;
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case ARM64_RELOC_PAGE21:
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case ARM64_RELOC_GOT_LOAD_PAGE21:
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case ARM64_RELOC_TLVP_LOAD_PAGE21:
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assert(r.pcrel);
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value = encodePage21(base, pageBits(value) - pageBits(pc));
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break;
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case ARM64_RELOC_PAGEOFF12:
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case ARM64_RELOC_GOT_LOAD_PAGEOFF12:
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case ARM64_RELOC_TLVP_LOAD_PAGEOFF12:
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assert(!r.pcrel);
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value = encodePageOff12(base, value);
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break;
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default:
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llvm_unreachable("unexpected relocation type");
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}
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switch (r.length) {
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case 2:
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write32le(loc, value);
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break;
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case 3:
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write64le(loc, value);
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break;
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default:
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llvm_unreachable("invalid r_length");
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}
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}
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static constexpr uint32_t stubCode[] = {
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0x90000010, // 00: adrp x16, __la_symbol_ptr@page
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0xf9400210, // 04: ldr x16, [x16, __la_symbol_ptr@pageoff]
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0xd61f0200, // 08: br x16
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};
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void ARM64::writeStub(uint8_t *buf8, const macho::Symbol &sym) const {
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auto *buf32 = reinterpret_cast<uint32_t *>(buf8);
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uint64_t pcPageBits =
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pageBits(in.stubs->addr + sym.stubsIndex * sizeof(stubCode));
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uint64_t lazyPointerVA = in.lazyPointers->addr + sym.stubsIndex * WordSize;
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buf32[0] = encodePage21(stubCode[0], pageBits(lazyPointerVA) - pcPageBits);
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buf32[1] = encodePageOff12(stubCode[1], lazyPointerVA);
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buf32[2] = stubCode[2];
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}
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static constexpr uint32_t stubHelperHeaderCode[] = {
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0x90000011, // 00: adrp x17, _dyld_private@page
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0x91000231, // 04: add x17, x17, _dyld_private@pageoff
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0xa9bf47f0, // 08: stp x16/x17, [sp, #-16]!
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0x90000010, // 0c: adrp x16, dyld_stub_binder@page
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0xf9400210, // 10: ldr x16, [x16, dyld_stub_binder@pageoff]
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0xd61f0200, // 14: br x16
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};
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void ARM64::writeStubHelperHeader(uint8_t *buf8) const {
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auto *buf32 = reinterpret_cast<uint32_t *>(buf8);
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auto pcPageBits = [](int i) {
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return pageBits(in.stubHelper->addr + i * sizeof(uint32_t));
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};
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uint64_t loaderVA = in.imageLoaderCache->getVA();
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buf32[0] =
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encodePage21(stubHelperHeaderCode[0], pageBits(loaderVA) - pcPageBits(0));
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buf32[1] = encodePageOff12(stubHelperHeaderCode[1], loaderVA);
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buf32[2] = stubHelperHeaderCode[2];
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uint64_t binderVA =
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in.got->addr + in.stubHelper->stubBinder->gotIndex * WordSize;
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buf32[3] =
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encodePage21(stubHelperHeaderCode[3], pageBits(binderVA) - pcPageBits(3));
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buf32[4] = encodePageOff12(stubHelperHeaderCode[4], binderVA);
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buf32[5] = stubHelperHeaderCode[5];
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}
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static constexpr uint32_t stubHelperEntryCode[] = {
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0x18000050, // 00: ldr w16, l0
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0x14000000, // 04: b stubHelperHeader
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0x00000000, // 08: l0: .long 0
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};
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void ARM64::writeStubHelperEntry(uint8_t *buf8, const DylibSymbol &sym,
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uint64_t entryVA) const {
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auto *buf32 = reinterpret_cast<uint32_t *>(buf8);
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auto pcVA = [entryVA](int i) { return entryVA + i * sizeof(uint32_t); };
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uint64_t stubHelperHeaderVA = in.stubHelper->addr;
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buf32[0] = stubHelperEntryCode[0];
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buf32[1] =
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encodeBranch26(stubHelperEntryCode[1], stubHelperHeaderVA - pcVA(1));
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buf32[2] = sym.lazyBindOffset;
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}
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void ARM64::relaxGotLoad(uint8_t *loc, uint8_t type) const {
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// The instruction format comments below are quoted from
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// Arm® Architecture Reference Manual
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// Armv8, for Armv8-A architecture profile
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// ARM DDI 0487G.a (ID011921)
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uint32_t instruction = read32le(loc);
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// C6.2.132 LDR (immediate)
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// LDR <Xt>, [<Xn|SP>{, #<pimm>}]
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if ((instruction & 0xffc00000) != 0xf9400000)
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error(getRelocAttrs(type).name + " reloc requires LDR instruction");
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assert(((instruction >> 10) & 0xfff) == 0 &&
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"non-zero embedded LDR immediate");
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// C6.2.4 ADD (immediate)
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// ADD <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}
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instruction = ((instruction & 0x001fffff) | 0x91000000);
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write32le(loc, instruction);
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}
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ARM64::ARM64() {
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cpuType = CPU_TYPE_ARM64;
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cpuSubtype = CPU_SUBTYPE_ARM64_ALL;
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stubSize = sizeof(stubCode);
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stubHelperHeaderSize = sizeof(stubHelperHeaderCode);
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stubHelperEntrySize = sizeof(stubHelperEntryCode);
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}
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TargetInfo *macho::createARM64TargetInfo() {
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static ARM64 t;
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return &t;
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}
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