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AArch64
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[CodeGen] Unify MBB reference format in both MIR and debug output
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2017-12-04 17:18:51 +00:00 |
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AMDGPU
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AMDGPU: Add num spilled s/vgprs to metadata
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2017-11-28 17:51:08 +00:00 |
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ARM
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[DWARFv5] Emit v5 line table header.
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2017-12-05 20:35:00 +00:00 |
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AVR
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[AVR] Use the short form of 'clr <reg>'
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2017-11-24 15:36:43 +00:00 |
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AsmParser
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[CodeGen] Unify MBB reference format in both MIR and debug output
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2017-12-04 17:18:51 +00:00 |
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BPF
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bpf: print backward branch target properly
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2017-11-16 19:15:36 +00:00 |
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COFF
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[CodeGen] Unify MBB reference format in both MIR and debug output
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2017-12-04 17:18:51 +00:00 |
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Disassembler
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[ARC] Add instruction subset for the ARC backend.
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2017-12-02 05:25:17 +00:00 |
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ELF
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Re-submit r289925 (Update .debug_line section version to match DWARF version)
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2017-12-04 21:27:46 +00:00 |
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Hexagon
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[Hexagon] Remove trailing spaces, NFC
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2017-11-22 20:43:00 +00:00 |
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Lanai
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[lanai] Add more tests for assembly of conditional ALU ops
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2016-07-11 17:58:16 +00:00 |
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MachO
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Re-submit r289925 (Update .debug_line section version to match DWARF version)
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2017-12-04 21:27:46 +00:00 |
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Markup
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…
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Mips
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[CodeGen] Unify MBB reference format in both MIR and debug output
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2017-12-04 17:18:51 +00:00 |
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PowerPC
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[CodeGen] Unify MBB reference format in both MIR and debug output
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2017-12-04 17:18:51 +00:00 |
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RISCV
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[RISCV] MC layer support for the standard RV32A instruction set extension
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2017-11-09 15:00:03 +00:00 |
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Sparc
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[Sparc] invalid adjustments in TLS_LE/TLS_LDO relocations removed
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2017-07-25 15:28:28 +00:00 |
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SystemZ
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[SystemZ, AsmParser] Enable the mnemonic spell corrector.
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2017-07-18 09:17:00 +00:00 |
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WebAssembly
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Reland "[WebAssembly] Add visibility flag to Wasm symbol flags""
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2017-12-03 01:19:23 +00:00 |
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X86
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[CodeGen] Unify MBB reference format in both MIR and debug output
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2017-12-04 17:18:51 +00:00 |
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