forked from OSchip/llvm-project
126 lines
4.4 KiB
C++
126 lines
4.4 KiB
C++
//===-- SparcMCTargetDesc.cpp - Sparc Target Descriptions -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides Sparc specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcMCTargetDesc.h"
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#include "InstPrinter/SparcInstPrinter.h"
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#include "SparcMCAsmInfo.h"
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#include "SparcTargetStreamer.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define GET_INSTRINFO_MC_DESC
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#include "SparcGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "SparcGenSubtargetInfo.inc"
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#define GET_REGINFO_MC_DESC
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#include "SparcGenRegisterInfo.inc"
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static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MRI,
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const Triple &TT) {
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MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT);
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unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
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MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
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MAI->addInitialFrameState(Inst);
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return MAI;
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}
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static MCAsmInfo *createSparcV9MCAsmInfo(const MCRegisterInfo &MRI,
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const Triple &TT) {
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MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT);
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unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
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MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 2047);
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MAI->addInitialFrameState(Inst);
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return MAI;
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}
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static MCInstrInfo *createSparcMCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitSparcMCInstrInfo(X);
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return X;
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}
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static MCRegisterInfo *createSparcMCRegisterInfo(const Triple &TT) {
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MCRegisterInfo *X = new MCRegisterInfo();
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InitSparcMCRegisterInfo(X, SP::O7);
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return X;
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}
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static MCSubtargetInfo *
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createSparcMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
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if (CPU.empty())
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CPU = (TT.getArch() == Triple::sparcv9) ? "v9" : "v8";
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return createSparcMCSubtargetInfoImpl(TT, CPU, FS);
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}
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static MCTargetStreamer *
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createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
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return new SparcTargetELFStreamer(S);
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}
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static MCTargetStreamer *createTargetAsmStreamer(MCStreamer &S,
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formatted_raw_ostream &OS,
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MCInstPrinter *InstPrint,
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bool isVerboseAsm) {
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return new SparcTargetAsmStreamer(S, OS);
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}
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static MCInstPrinter *createSparcMCInstPrinter(const Triple &T,
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unsigned SyntaxVariant,
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const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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const MCRegisterInfo &MRI) {
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return new SparcInstPrinter(MAI, MII, MRI);
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}
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extern "C" void LLVMInitializeSparcTargetMC() {
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// Register the MC asm info.
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RegisterMCAsmInfoFn X(getTheSparcTarget(), createSparcMCAsmInfo);
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RegisterMCAsmInfoFn Y(getTheSparcV9Target(), createSparcV9MCAsmInfo);
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RegisterMCAsmInfoFn Z(getTheSparcelTarget(), createSparcMCAsmInfo);
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for (Target *T :
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{&getTheSparcTarget(), &getTheSparcV9Target(), &getTheSparcelTarget()}) {
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// Register the MC instruction info.
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TargetRegistry::RegisterMCInstrInfo(*T, createSparcMCInstrInfo);
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// Register the MC register info.
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TargetRegistry::RegisterMCRegInfo(*T, createSparcMCRegisterInfo);
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// Register the MC subtarget info.
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TargetRegistry::RegisterMCSubtargetInfo(*T, createSparcMCSubtargetInfo);
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// Register the MC Code Emitter.
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TargetRegistry::RegisterMCCodeEmitter(*T, createSparcMCCodeEmitter);
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// Register the asm backend.
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TargetRegistry::RegisterMCAsmBackend(*T, createSparcAsmBackend);
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// Register the object target streamer.
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TargetRegistry::RegisterObjectTargetStreamer(*T,
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createObjectTargetStreamer);
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// Register the asm streamer.
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TargetRegistry::RegisterAsmTargetStreamer(*T, createTargetAsmStreamer);
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// Register the MCInstPrinter
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TargetRegistry::RegisterMCInstPrinter(*T, createSparcMCInstPrinter);
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}
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}
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