forked from OSchip/llvm-project
516 lines
16 KiB
C++
516 lines
16 KiB
C++
//===-- AMDGPUCodeGenPrepare.cpp ------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This pass does misc. AMDGPU optimizations on IR before instruction
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/// selection.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUIntrinsicInfo.h"
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#include "AMDGPUSubtarget.h"
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#include "AMDGPUTargetMachine.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Analysis/DivergenceAnalysis.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/BasicBlock.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/InstrTypes.h"
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#include "llvm/IR/Instruction.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/InstVisitor.h"
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/IR/Operator.h"
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#include "llvm/IR/Type.h"
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#include "llvm/IR/Value.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/Casting.h"
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#include <cassert>
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#include <iterator>
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#define DEBUG_TYPE "amdgpu-codegenprepare"
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using namespace llvm;
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namespace {
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class AMDGPUCodeGenPrepare : public FunctionPass,
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public InstVisitor<AMDGPUCodeGenPrepare, bool> {
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const GCNTargetMachine *TM;
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const SISubtarget *ST = nullptr;
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DivergenceAnalysis *DA = nullptr;
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Module *Mod = nullptr;
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bool HasUnsafeFPMath = false;
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/// \brief Copies exact/nsw/nuw flags (if any) from binary operation \p I to
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/// binary operation \p V.
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///
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/// \returns Binary operation \p V.
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/// \returns \p T's base element bit width.
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unsigned getBaseElementBitWidth(const Type *T) const;
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/// \returns Equivalent 32 bit integer type for given type \p T. For example,
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/// if \p T is i7, then i32 is returned; if \p T is <3 x i12>, then <3 x i32>
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/// is returned.
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Type *getI32Ty(IRBuilder<> &B, const Type *T) const;
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/// \returns True if binary operation \p I is a signed binary operation, false
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/// otherwise.
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bool isSigned(const BinaryOperator &I) const;
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/// \returns True if the condition of 'select' operation \p I comes from a
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/// signed 'icmp' operation, false otherwise.
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bool isSigned(const SelectInst &I) const;
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/// \returns True if type \p T needs to be promoted to 32 bit integer type,
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/// false otherwise.
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bool needsPromotionToI32(const Type *T) const;
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/// \brief Promotes uniform binary operation \p I to equivalent 32 bit binary
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/// operation.
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///
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/// \details \p I's base element bit width must be greater than 1 and less
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/// than or equal 16. Promotion is done by sign or zero extending operands to
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/// 32 bits, replacing \p I with equivalent 32 bit binary operation, and
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/// truncating the result of 32 bit binary operation back to \p I's original
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/// type. Division operation is not promoted.
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///
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/// \returns True if \p I is promoted to equivalent 32 bit binary operation,
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/// false otherwise.
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bool promoteUniformOpToI32(BinaryOperator &I) const;
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/// \brief Promotes uniform 'icmp' operation \p I to 32 bit 'icmp' operation.
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///
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/// \details \p I's base element bit width must be greater than 1 and less
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/// than or equal 16. Promotion is done by sign or zero extending operands to
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/// 32 bits, and replacing \p I with 32 bit 'icmp' operation.
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///
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/// \returns True.
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bool promoteUniformOpToI32(ICmpInst &I) const;
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/// \brief Promotes uniform 'select' operation \p I to 32 bit 'select'
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/// operation.
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///
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/// \details \p I's base element bit width must be greater than 1 and less
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/// than or equal 16. Promotion is done by sign or zero extending operands to
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/// 32 bits, replacing \p I with 32 bit 'select' operation, and truncating the
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/// result of 32 bit 'select' operation back to \p I's original type.
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///
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/// \returns True.
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bool promoteUniformOpToI32(SelectInst &I) const;
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/// \brief Promotes uniform 'bitreverse' intrinsic \p I to 32 bit 'bitreverse'
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/// intrinsic.
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///
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/// \details \p I's base element bit width must be greater than 1 and less
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/// than or equal 16. Promotion is done by zero extending the operand to 32
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/// bits, replacing \p I with 32 bit 'bitreverse' intrinsic, shifting the
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/// result of 32 bit 'bitreverse' intrinsic to the right with zero fill (the
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/// shift amount is 32 minus \p I's base element bit width), and truncating
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/// the result of the shift operation back to \p I's original type.
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///
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/// \returns True.
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bool promoteUniformBitreverseToI32(IntrinsicInst &I) const;
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public:
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static char ID;
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AMDGPUCodeGenPrepare(const TargetMachine *TM = nullptr) :
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FunctionPass(ID), TM(static_cast<const GCNTargetMachine *>(TM)) {}
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bool visitFDiv(BinaryOperator &I);
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bool visitInstruction(Instruction &I) { return false; }
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bool visitBinaryOperator(BinaryOperator &I);
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bool visitICmpInst(ICmpInst &I);
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bool visitSelectInst(SelectInst &I);
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bool visitIntrinsicInst(IntrinsicInst &I);
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bool visitBitreverseIntrinsicInst(IntrinsicInst &I);
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bool doInitialization(Module &M) override;
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bool runOnFunction(Function &F) override;
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StringRef getPassName() const override { return "AMDGPU IR optimizations"; }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<DivergenceAnalysis>();
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AU.setPreservesAll();
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}
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};
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} // end anonymous namespace
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unsigned AMDGPUCodeGenPrepare::getBaseElementBitWidth(const Type *T) const {
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assert(needsPromotionToI32(T) && "T does not need promotion to i32");
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if (T->isIntegerTy())
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return T->getIntegerBitWidth();
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return cast<VectorType>(T)->getElementType()->getIntegerBitWidth();
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}
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Type *AMDGPUCodeGenPrepare::getI32Ty(IRBuilder<> &B, const Type *T) const {
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assert(needsPromotionToI32(T) && "T does not need promotion to i32");
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if (T->isIntegerTy())
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return B.getInt32Ty();
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return VectorType::get(B.getInt32Ty(), cast<VectorType>(T)->getNumElements());
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}
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bool AMDGPUCodeGenPrepare::isSigned(const BinaryOperator &I) const {
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return I.getOpcode() == Instruction::AShr ||
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I.getOpcode() == Instruction::SDiv || I.getOpcode() == Instruction::SRem;
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}
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bool AMDGPUCodeGenPrepare::isSigned(const SelectInst &I) const {
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return isa<ICmpInst>(I.getOperand(0)) ?
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cast<ICmpInst>(I.getOperand(0))->isSigned() : false;
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}
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bool AMDGPUCodeGenPrepare::needsPromotionToI32(const Type *T) const {
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if (T->isIntegerTy() && T->getIntegerBitWidth() > 1 &&
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T->getIntegerBitWidth() <= 16)
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return true;
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if (!T->isVectorTy())
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return false;
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return needsPromotionToI32(cast<VectorType>(T)->getElementType());
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}
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// Return true if the op promoted to i32 should have nsw set.
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static bool promotedOpIsNSW(const Instruction &I) {
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switch (I.getOpcode()) {
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case Instruction::Shl:
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case Instruction::Add:
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case Instruction::Sub:
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return true;
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case Instruction::Mul:
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return I.hasNoUnsignedWrap();
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default:
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return false;
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}
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}
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// Return true if the op promoted to i32 should have nuw set.
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static bool promotedOpIsNUW(const Instruction &I) {
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switch (I.getOpcode()) {
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case Instruction::Shl:
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case Instruction::Add:
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case Instruction::Mul:
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return true;
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case Instruction::Sub:
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return I.hasNoUnsignedWrap();
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default:
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return false;
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}
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}
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bool AMDGPUCodeGenPrepare::promoteUniformOpToI32(BinaryOperator &I) const {
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assert(needsPromotionToI32(I.getType()) &&
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"I does not need promotion to i32");
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if (I.getOpcode() == Instruction::SDiv ||
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I.getOpcode() == Instruction::UDiv)
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return false;
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IRBuilder<> Builder(&I);
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Builder.SetCurrentDebugLocation(I.getDebugLoc());
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Type *I32Ty = getI32Ty(Builder, I.getType());
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Value *ExtOp0 = nullptr;
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Value *ExtOp1 = nullptr;
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Value *ExtRes = nullptr;
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Value *TruncRes = nullptr;
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if (isSigned(I)) {
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ExtOp0 = Builder.CreateSExt(I.getOperand(0), I32Ty);
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ExtOp1 = Builder.CreateSExt(I.getOperand(1), I32Ty);
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} else {
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ExtOp0 = Builder.CreateZExt(I.getOperand(0), I32Ty);
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ExtOp1 = Builder.CreateZExt(I.getOperand(1), I32Ty);
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}
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ExtRes = Builder.CreateBinOp(I.getOpcode(), ExtOp0, ExtOp1);
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if (Instruction *Inst = dyn_cast<Instruction>(ExtRes)) {
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if (promotedOpIsNSW(cast<Instruction>(I)))
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Inst->setHasNoSignedWrap();
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if (promotedOpIsNUW(cast<Instruction>(I)))
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Inst->setHasNoUnsignedWrap();
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if (const auto *ExactOp = dyn_cast<PossiblyExactOperator>(&I))
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Inst->setIsExact(ExactOp->isExact());
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}
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TruncRes = Builder.CreateTrunc(ExtRes, I.getType());
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I.replaceAllUsesWith(TruncRes);
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I.eraseFromParent();
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return true;
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}
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bool AMDGPUCodeGenPrepare::promoteUniformOpToI32(ICmpInst &I) const {
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assert(needsPromotionToI32(I.getOperand(0)->getType()) &&
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"I does not need promotion to i32");
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IRBuilder<> Builder(&I);
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Builder.SetCurrentDebugLocation(I.getDebugLoc());
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Type *I32Ty = getI32Ty(Builder, I.getOperand(0)->getType());
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Value *ExtOp0 = nullptr;
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Value *ExtOp1 = nullptr;
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Value *NewICmp = nullptr;
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if (I.isSigned()) {
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ExtOp0 = Builder.CreateSExt(I.getOperand(0), I32Ty);
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ExtOp1 = Builder.CreateSExt(I.getOperand(1), I32Ty);
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} else {
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ExtOp0 = Builder.CreateZExt(I.getOperand(0), I32Ty);
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ExtOp1 = Builder.CreateZExt(I.getOperand(1), I32Ty);
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}
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NewICmp = Builder.CreateICmp(I.getPredicate(), ExtOp0, ExtOp1);
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I.replaceAllUsesWith(NewICmp);
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I.eraseFromParent();
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return true;
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}
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bool AMDGPUCodeGenPrepare::promoteUniformOpToI32(SelectInst &I) const {
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assert(needsPromotionToI32(I.getType()) &&
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"I does not need promotion to i32");
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IRBuilder<> Builder(&I);
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Builder.SetCurrentDebugLocation(I.getDebugLoc());
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Type *I32Ty = getI32Ty(Builder, I.getType());
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Value *ExtOp1 = nullptr;
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Value *ExtOp2 = nullptr;
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Value *ExtRes = nullptr;
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Value *TruncRes = nullptr;
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if (isSigned(I)) {
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ExtOp1 = Builder.CreateSExt(I.getOperand(1), I32Ty);
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ExtOp2 = Builder.CreateSExt(I.getOperand(2), I32Ty);
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} else {
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ExtOp1 = Builder.CreateZExt(I.getOperand(1), I32Ty);
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ExtOp2 = Builder.CreateZExt(I.getOperand(2), I32Ty);
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}
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ExtRes = Builder.CreateSelect(I.getOperand(0), ExtOp1, ExtOp2);
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TruncRes = Builder.CreateTrunc(ExtRes, I.getType());
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I.replaceAllUsesWith(TruncRes);
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I.eraseFromParent();
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return true;
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}
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bool AMDGPUCodeGenPrepare::promoteUniformBitreverseToI32(
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IntrinsicInst &I) const {
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assert(I.getIntrinsicID() == Intrinsic::bitreverse &&
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"I must be bitreverse intrinsic");
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assert(needsPromotionToI32(I.getType()) &&
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"I does not need promotion to i32");
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IRBuilder<> Builder(&I);
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Builder.SetCurrentDebugLocation(I.getDebugLoc());
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Type *I32Ty = getI32Ty(Builder, I.getType());
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Function *I32 =
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Intrinsic::getDeclaration(Mod, Intrinsic::bitreverse, { I32Ty });
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Value *ExtOp = Builder.CreateZExt(I.getOperand(0), I32Ty);
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Value *ExtRes = Builder.CreateCall(I32, { ExtOp });
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Value *LShrOp =
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Builder.CreateLShr(ExtRes, 32 - getBaseElementBitWidth(I.getType()));
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Value *TruncRes =
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Builder.CreateTrunc(LShrOp, I.getType());
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I.replaceAllUsesWith(TruncRes);
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I.eraseFromParent();
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return true;
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}
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static bool shouldKeepFDivF32(Value *Num, bool UnsafeDiv) {
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const ConstantFP *CNum = dyn_cast<ConstantFP>(Num);
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if (!CNum)
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return false;
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// Reciprocal f32 is handled separately without denormals.
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return UnsafeDiv || CNum->isExactlyValue(+1.0);
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}
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// Insert an intrinsic for fast fdiv for safe math situations where we can
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// reduce precision. Leave fdiv for situations where the generic node is
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// expected to be optimized.
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bool AMDGPUCodeGenPrepare::visitFDiv(BinaryOperator &FDiv) {
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Type *Ty = FDiv.getType();
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if (!Ty->getScalarType()->isFloatTy())
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return false;
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MDNode *FPMath = FDiv.getMetadata(LLVMContext::MD_fpmath);
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if (!FPMath)
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return false;
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const FPMathOperator *FPOp = cast<const FPMathOperator>(&FDiv);
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float ULP = FPOp->getFPAccuracy();
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if (ULP < 2.5f)
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return false;
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FastMathFlags FMF = FPOp->getFastMathFlags();
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bool UnsafeDiv = HasUnsafeFPMath || FMF.unsafeAlgebra() ||
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FMF.allowReciprocal();
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if (ST->hasFP32Denormals() && !UnsafeDiv)
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return false;
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IRBuilder<> Builder(FDiv.getParent(), std::next(FDiv.getIterator()), FPMath);
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Builder.setFastMathFlags(FMF);
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Builder.SetCurrentDebugLocation(FDiv.getDebugLoc());
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const AMDGPUIntrinsicInfo *II = TM->getIntrinsicInfo();
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Function *Decl
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= II->getDeclaration(Mod, AMDGPUIntrinsic::amdgcn_fdiv_fast, {});
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Value *Num = FDiv.getOperand(0);
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Value *Den = FDiv.getOperand(1);
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Value *NewFDiv = nullptr;
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if (VectorType *VT = dyn_cast<VectorType>(Ty)) {
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NewFDiv = UndefValue::get(VT);
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// FIXME: Doesn't do the right thing for cases where the vector is partially
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// constant. This works when the scalarizer pass is run first.
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for (unsigned I = 0, E = VT->getNumElements(); I != E; ++I) {
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Value *NumEltI = Builder.CreateExtractElement(Num, I);
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Value *DenEltI = Builder.CreateExtractElement(Den, I);
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Value *NewElt;
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if (shouldKeepFDivF32(NumEltI, UnsafeDiv)) {
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NewElt = Builder.CreateFDiv(NumEltI, DenEltI);
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} else {
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NewElt = Builder.CreateCall(Decl, { NumEltI, DenEltI });
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}
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NewFDiv = Builder.CreateInsertElement(NewFDiv, NewElt, I);
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}
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} else {
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if (!shouldKeepFDivF32(Num, UnsafeDiv))
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NewFDiv = Builder.CreateCall(Decl, { Num, Den });
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}
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if (NewFDiv) {
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FDiv.replaceAllUsesWith(NewFDiv);
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NewFDiv->takeName(&FDiv);
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FDiv.eraseFromParent();
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}
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return true;
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}
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static bool hasUnsafeFPMath(const Function &F) {
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Attribute Attr = F.getFnAttribute("unsafe-fp-math");
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return Attr.getValueAsString() == "true";
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}
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bool AMDGPUCodeGenPrepare::visitBinaryOperator(BinaryOperator &I) {
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bool Changed = false;
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if (ST->has16BitInsts() && needsPromotionToI32(I.getType()) &&
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DA->isUniform(&I))
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Changed |= promoteUniformOpToI32(I);
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return Changed;
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}
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bool AMDGPUCodeGenPrepare::visitICmpInst(ICmpInst &I) {
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bool Changed = false;
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if (ST->has16BitInsts() && needsPromotionToI32(I.getOperand(0)->getType()) &&
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DA->isUniform(&I))
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Changed |= promoteUniformOpToI32(I);
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return Changed;
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}
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bool AMDGPUCodeGenPrepare::visitSelectInst(SelectInst &I) {
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bool Changed = false;
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if (ST->has16BitInsts() && needsPromotionToI32(I.getType()) &&
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DA->isUniform(&I))
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Changed |= promoteUniformOpToI32(I);
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return Changed;
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}
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bool AMDGPUCodeGenPrepare::visitIntrinsicInst(IntrinsicInst &I) {
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switch (I.getIntrinsicID()) {
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case Intrinsic::bitreverse:
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return visitBitreverseIntrinsicInst(I);
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default:
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return false;
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}
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}
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bool AMDGPUCodeGenPrepare::visitBitreverseIntrinsicInst(IntrinsicInst &I) {
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bool Changed = false;
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if (ST->has16BitInsts() && needsPromotionToI32(I.getType()) &&
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DA->isUniform(&I))
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Changed |= promoteUniformBitreverseToI32(I);
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return Changed;
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}
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bool AMDGPUCodeGenPrepare::doInitialization(Module &M) {
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Mod = &M;
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return false;
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}
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bool AMDGPUCodeGenPrepare::runOnFunction(Function &F) {
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if (!TM || skipFunction(F))
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return false;
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ST = &TM->getSubtarget<SISubtarget>(F);
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DA = &getAnalysis<DivergenceAnalysis>();
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HasUnsafeFPMath = hasUnsafeFPMath(F);
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bool MadeChange = false;
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for (BasicBlock &BB : F) {
|
|
BasicBlock::iterator Next;
|
|
for (BasicBlock::iterator I = BB.begin(), E = BB.end(); I != E; I = Next) {
|
|
Next = std::next(I);
|
|
MadeChange |= visit(*I);
|
|
}
|
|
}
|
|
|
|
return MadeChange;
|
|
}
|
|
|
|
INITIALIZE_TM_PASS_BEGIN(AMDGPUCodeGenPrepare, DEBUG_TYPE,
|
|
"AMDGPU IR optimizations", false, false)
|
|
INITIALIZE_PASS_DEPENDENCY(DivergenceAnalysis)
|
|
INITIALIZE_TM_PASS_END(AMDGPUCodeGenPrepare, DEBUG_TYPE,
|
|
"AMDGPU IR optimizations", false, false)
|
|
|
|
char AMDGPUCodeGenPrepare::ID = 0;
|
|
|
|
FunctionPass *llvm::createAMDGPUCodeGenPreparePass(const GCNTargetMachine *TM) {
|
|
return new AMDGPUCodeGenPrepare(TM);
|
|
}
|