Craig Topper 25ea4e5ad3 Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen ... llvm-svn: 142105		2011-10-16 03:51:13 +00:00
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dg.exp	…
enhanced.txt	Insert dummy ED table entries for pseudo-instructions.	2011-10-10 18:30:16 +00:00
intel-syntax.txt	Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST.	2011-10-02 21:08:12 +00:00
invalid-VEX-vvvv.txt	Add test case for PR10851.	2011-09-14 04:36:54 +00:00
simple-tests.txt	Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen	2011-10-16 03:51:13 +00:00
truncated-input.txt	…
x86-32.txt	Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen	2011-10-16 03:51:13 +00:00