Craig Topper 25ea4e5ad3 Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen ... llvm-svn: 142105		2011-10-16 03:51:13 +00:00
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ARM	Thumb2 assembly parsing and encoding for LDC/STC.	2011-10-12 20:54:17 +00:00
MBlaze	Teach the MBlaze disassembler to disassemble special purpose registers.	2010-12-20 21:18:04 +00:00
X86	Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen	2011-10-16 03:51:13 +00:00