forked from OSchip/llvm-project
6d760d7cb3
Eventually this pass will provide substantially better code in the interim between when we have a crappy isel and nice isel. Unfortunately doing so requires fixing the backend to actually SUPPORT all of the fancy addressing modes that we now generate, and writing a DCE pass for machine code. Each of these is a fairly substantial job, so this will remain disabled for the immediate future. :( llvm-svn: 10276 |
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.. | ||
Sparc | ||
X86 | ||
MRegisterInfo.cpp | ||
Makefile | ||
Target.td | ||
TargetData.cpp | ||
TargetInstrInfo.cpp | ||
TargetMachine.cpp | ||
TargetSchedInfo.cpp |